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Intel(R) Wireless Flash Memory (W18)
28F320W18, 28F640W18, 28F128W18
Datasheet
Product Features
High Performance Read-While-Write/ Erase -- Burst frequency at 66 MHz -- 60 ns Initial Access Read Speed -- 11 ns Burst-Mode Read Speed -- 20 ns Page-Mode Read Speed -- 4-, 8-, 16-, and Continuous-Word Burst Mode Reads -- Burst and Page Mode Reads in all Blocks, across all partition boundaries -- Burst Suspend Feature -- Enhanced Factory Programming at 3.1 s/word (typ.for 0.13 m) Security -- 128-bit Protection Register -- 64-bits Unique Programmed by Intel -- 64-bits User-Programmable -- Absolute Write Protection with VPP at Ground -- Individual and Instantaneous Block Locking/Unlocking with Lock-Down Capability Quality and Reliability -- Temperature Range: -40 C to +85 C -- 100k Erase Cycles per Block -- 0.13 m ETOXTM VIII Process -- 0.18 m ETOXTM VII Process
Architecture -- Multiple 4-Mbit Partitions -- Dual Operation: RWW or RWE -- 8KB parameter blocks -- 64KB main blocks -- Top or Bottom Parameter Devices -- 16-bit wide data bus Software -- 5 s (typ.) Program and Erase Suspend Latency Time -- Flash Data Integrator (FDI) and Common Flash Interface (CFI) Compatible -- Programmable WAIT Signal Polarity Packaging and Power -- 0.13 m: 32-, 64-, and 128-Mbit in VF BGA Package; 128-Mbit in QUAD+ Package -- 0.18 m: 32- and 128-Mbit Densities in VF BGA Package; 64-Mbit Density in BGA* Package -- 56 Active Ball Matrix, 0.75 mm BallPitch -- VCC = 1.70 V to 1.95 V -- VCCQ = 1.70 V to 2.24 V or 1.35 V to 1.80 V -- Standby current (0.13 m): 8A (typ.) -- Read current: 7mA (typ.)
The Intel(R) Wireless Flash Memory (W18) device with flexible multi-partition dual operation, provides high-performance asynchronous and synchronous burst reads. It is an ideal memory for low-voltage burst CPUs. Combining high read performance with flash memory's intrinsic nonvolatility, the W18 device eliminates the traditional system-performance paradigm of shadowing redundant code memory from slow nonvolatile storage to faster execution memory. It reduces the total memory requirement that increases reliability and reduces overall system power consumption and cost. The W18 device's flexible multi-partition architecture allows programming or erasing to occur in one partition while reading from another partition. This allows for higher data write throughput compared to single partition architectures. The dual-operation architecture also allows two processors to interleave code operations while program and erase operations take place in the background. The designer can also choose the size of the code and data partitions via the flexible multi-partition architecture.
Notice: This document contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
290701-009 December 2003
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 1.8 Volt Intel(R) wireless flash memory datasheet may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) 2003, Intel Corporation. *Other names and brands may be claimed as the property of others.
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Contents
Contents
1.0 Introduction ...............................................................................................................................9
1.1 1.2 1.3 2.1 2.2 2.3 2.4 3.1 Document Purpose ...............................................................................................................9 Nomenclature .......................................................................................................................9 Conventions..........................................................................................................................9 Product Overview ...............................................................................................................10 Package Diagram ...............................................................................................................12 Signal Descriptions .............................................................................................................14 Memory Map and Partitioning .............................................................................................15 Bus Operations ...................................................................................................................18 3.1.1 Read ......................................................................................................................18 3.1.2 Burst Suspend .......................................................................................................19 3.1.3 Standby..................................................................................................................19 3.1.4 Reset .....................................................................................................................19 3.1.5 Write ......................................................................................................................20 Device Commands .............................................................................................................20 Command Sequencing .......................................................................................................24 Read Array..........................................................................................................................25 Read Device ID...................................................................................................................25 Read Query (CFI) ...............................................................................................................26 Read Status Register..........................................................................................................26 Clear Status Register..........................................................................................................28 Word Program ....................................................................................................................28 Factory Programming .........................................................................................................29 Enhanced Factory Program (EFP) .....................................................................................30 5.3.1 EFP Requirements and Considerations.................................................................30 5.3.2 Setup .....................................................................................................................31 5.3.3 Program .................................................................................................................31 5.3.4 Verify......................................................................................................................31 5.3.5 Exit.........................................................................................................................32 Program/Erase Suspend and Resume ...............................................................................34 Block Erase.........................................................................................................................36 Read-While-Write and Read-While-Erase ..........................................................................38 Block Lock Operations ........................................................................................................39 7.1.1 Lock .......................................................................................................................40 7.1.2 Unlock ....................................................................................................................40
2.0 Device Description................................................................................................................10
3.0 Device Operations.................................................................................................................18
3.2 3.3 4.1 4.2 4.3 4.4 4.5 5.1 5.2 5.3
4.0 Read Operations ....................................................................................................................25
5.0 Program Operations.............................................................................................................28
6.0 Program and Erase Operations .......................................................................................34
6.1 6.2 6.3 7.1
7.0 Security Modes.......................................................................................................................39
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Contents
7.2
7.3
7.1.3 Lock-Down............................................................................................................. 40 7.1.4 Block Lock Status .................................................................................................. 41 7.1.5 Lock During Erase Suspend .................................................................................. 41 7.1.6 Status Register Error Checking ............................................................................. 41 7.1.7 WP# Lock-Down Control ....................................................................................... 42 Protection Register ............................................................................................................. 42 7.2.1 Reading the Protection Register............................................................................ 43 7.2.2 Programing the Protection Register....................................................................... 43 7.2.3 Locking the Protection Register............................................................................. 44 VPP Protection ................................................................................................................... 45
8.0 Set Configuration Register................................................................................................ 46
8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 9.1 9.2 9.3 9.4 Read Mode (CR[15])........................................................................................................... 48 First Access Latency Count (CR[13:11]) ............................................................................ 48 8.2.1 Latency Count Settings.......................................................................................... 49 WAIT Signal Polarity (CR[10]) ............................................................................................ 50 WAIT Signal Function ......................................................................................................... 50 Data Hold (CR[9]) ............................................................................................................... 51 WAIT Delay (CR[8]) ............................................................................................................ 52 Burst Sequence (CR[7])...................................................................................................... 52 Clock Edge (CR[6])............................................................................................................. 54 Burst Wrap (CR[3]) ............................................................................................................. 54 Burst Length (CR[2:0])........................................................................................................ 54 Active Power....................................................................................................................... 55 Automatic Power Savings (APS) ........................................................................................ 55 Standby Power ................................................................................................................... 55 Power-Up/Down Characteristics......................................................................................... 55 9.4.1 System Reset and RST# ....................................................................................... 56 9.4.2 VCC, VPP, and RST# Transitions ......................................................................... 56 Power Supply Decoupling................................................................................................... 56 Absolute Maximum Ratings ................................................................................................ 57 Operating Conditions .......................................................................................................... 57 DC Current Characteristics (.13 and .18 )................................................................. 58 DC Voltage Characteristics................................................................................................. 60 Read Operations - .13 ............................................................................ 62 Read Operations - .18 ............................................................................ 64 AC Write Characteristics..................................................................................................... 74 Erase and Program Times.................................................................................................. 79 Reset Specifications ........................................................................................................... 80 AC I/O Test Conditions ....................................................................................................... 81 Device Capacitance............................................................................................................ 82
9.0 Power Consumption............................................................................................................. 55
9.5 10.1 10.2 10.3 10.4 11.1 11.2 11.3 11.4 11.5 11.6 11.7
10.0 Thermal and DC Characteristics ..................................................................................... 57
11.0 AC Characteristics................................................................................................................ 62
Appendix A Write State Machine States ............................................................................... 83 Appendix B Common Flash Interface.................................................................................... 86
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Appendix C Mechanical Specifications.................................................................................95 Appendix D Ordering Information .........................................................................................100
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Revision History
Date of Revision 09/13/00 Version -001 Initial Release Deleted 16-Mbit density Revised ADV#, Section 2.2 Revised Protection Registers, Section 4.16 Revised Program Protection Register, Section 4.18 Revised Example in First Access Latency Count, Section 5.0.2 Revised Figure 5, Data Output with LC Setting at Code 3 Added WAIT Signal Function, Section 5.0.3 Revised WAIT Signal Polarity, Section 5.0.4 Revised Data Output Configuration, Section 5.0.5 Added Figure 7, Data Output Configuration with WAIT Signal Delay Revised WAIT Delay Configuration, Section 5.0.6 Changed VCCQ Spec from 1.7 V - 1.95 V to 1.7 V - 2.24 V in Section 8.2, Extended Temperature Operation 01/29/01 -002 Changed ICCS Spec from 15 A to 18 A in Section 8.4, DC Characteristics Changed ICCR Spec from 10 mA (CLK = 40 MHz, burst length = 4) and 13 mA (CLK = 52 MHz, burst length = 4) to 13 mA, and 16 mA respectively in Section 8.4, DC Characteristics Changed ICCWS Spec from 15 A to 18 A in Section 8.4, DC Characteristics Changed ICCES Spec from 15 A to 18 A in Section 8.4, DC Characteristics Changed tCHQX Spec from 5ns to 3ns in Section 8.6, AC Read Characteristics Added Figure 25, WAIT Signal in Synchronous Non-Read Array Operation Waveform Added Figure 26, WAIT Signal in Asynchronous Page Mode Read Operation Waveform Added Figure 27, WAIT Signal in Asynchronous Single Word Read Operation Waveform Revised Appendix E, Ordering Information Revised entire Section 4.10, Enhanced Factory Program Command (EFP) and Figure 6, Enhanced Factory Program Flowchart Revised Section 4.13, Protection Register Revised Section 4.15, Program Protection Register Revised Section 7.3, Capacitance, to include 128-Mbit specs 06/12/01 -003 Revised Section 7.4, DC Characteristics, to include 128-Mbit specs Revised Section 7.6, AC Read Characteristics, to include 128-Mbit device specifications Added tVHGL Spec in Section 7.6, AC Read Characteristics Revised Section 7.7, AC Write Characteristics, to include 128-Mbit device specifications Minor text edits Description
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Date of Revision
Version New Sections Organization Added 16 Word Burst Feature Added Burst Suspend Section
Description
Revised Block Locking State Diagram Revised Active Power Section Revised Automatic Power Savings Section Revised Power-Up/Down Operation Section Revised Extended Temperature Operation 04/05/02 -004 Added 128Mb DC Characteristics Table Added 128 Mb AC Read Characteristics Revised Table 17. Test Configuration Component Values for Worst Case Speed Conditions Added .13 Product DC and AC Read Characteristics Revised AC Write Characteristics Added Read to Write and Write to Read Transition Waveforms Revised Reset Specifications Various text edits Various text edits 10/10/02 -005 Updated Latency Count Section, including adding Latency Count Tables Added section 8.4 WAIT Function and WAIT Summary Table Updated Package Drawing and Dimensions 11/12/02 -006 Various text clarifications Removed Intel Burst Order 01/14/03 -007 Revised Table 22, DC Current Characteristics, ICCS Revised Table 22, DC Current Characteristics, ICCAPS Various text edits Revised Table 22, Read Operations, tAPA 03/21/03 -008 Added note to table 15, Configuration Register Descriptions Added note to section 3.1.1, Read Updated Block-Lock Operations (Section 7.1 and Figure 11) Updated Table 21 (128Mb ICCR) 12/17/03 -009 Updated Table 4 (WAIT behavior) Added QUAD+ ballout, package mechanicals, and order information Various text edits including latest product-naming convention
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Datasheet
Intel(R) Wireless Flash Memory (W18)
1.0
1.1
Introduction
Document Purpose
This datasheet contains information about the 1.8 Volt Intel(R) Wireless Flash memory (W18) device family. Section 1.0 provides a flash memory overview. Section 2.0 through Section 9.0 describe the memory functionality. Section 10.0 describes the electrical specifications for extended temperature product offerings. Packaging specifications and order information can be found in Appendix C and Appendix D, respectively.
1.2
Nomenclature
Many acronyms that describe product features or usage are defined here:
* * * * * * * * * * * * * *
APS - Automatic Power Savings BBA - Block Base Address CFI - Common Flash Interface CUI - Command User Interface EFP - Enhanced Factory Programming FDI - Flash Data Integrator NC - No Connect OTP - One-Time Programmable PBA - Partition Base Address RWE - Read-While-Erase RWW - Read-While-Write SRD - Status Register Data VF BGA - Very thin, Fine pitch, Ball Grid Array WSM - Write State Machine
1.3
Conventions
Many abbreviated terms and phrases are used throughout this document:
* The term "1.8 V" refers to the full VCC voltage range of 1.7 V - 1.95 V (except where noted)
and "VPP = 12 V" refers to 12 V 5%.
* When referring to registers, the term set means the bit is a logical 1, and clear means the bit is
a logical 0.
* The terms pin and signal are often used interchangeably to refer to the external signal
connections on the package. (ball is the term used for VF BGA).
* A word is 2 bytes, or 16 bits.
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Intel(R) Wireless Flash Memory (W18)
* Signal names are in all CAPS (see Section 2.3, "Signal Descriptions" on page 14.) * Voltage applied to the signal is subscripted, for example, VPP.
Throughout this document, references are made to top, bottom, parameter, and partition. To clarify these references, the following conventions have been adopted:
* A block is a group of bits (or words) that erase simultaneously with one block erase
instruction.
* * * *
A main block contains 32 Kwords. A parameter block contains 4 Kwords. The Block Base Address (BBA) is the first address of a block. A partition is a group of blocks that share erase and program circuitry and a common status register. Mbit top-parameter device, partition number 5 has a PBA of 140000h.
* The Partition Base Address (PBA) is the first address of a partition. For example, on a 32* The top partition is located at the highest physical device address. This partition may be a
main partition or a parameter partition.
* The bottom partition is located at the lowest physical device address. This partition may be a
main partition or a parameter partition.
* A main partition contains only main blocks. * A parameter partition contains a mixture of main blocks and parameter blocks. * A top parameter device (TPD) has the parameter partition at the top of the memory map with
the parameter blocks at the top of that partition. This was formerly referred to as top-boot device.
* A bottom parameter device (BPD) has the parameter partition at the bottom of the memory
map with the parameter blocks at the bottom of that partition. This was formerly referred to as bottom-boot block flash device.
2.0
Device Description
This section provides an overview of the W18 device features, packaging, signal naming, and device architecture.
2.1
Product Overview
The W18 device provides Read-While-Write (RWW) and Read-White-Erase (RWE) capability with high-performance synchronous and asynchronous reads on package-compatible densities with a 16-bit data bus. Individually-erasable memory blocks are optimally sized for code and data storage. Eight 4-Kword parameter blocks are located in the parameter partition at either the top or bottom of the memory map. The rest of the memory array is grouped into 32-Kword main blocks. The memory architecture for the W18 device consists of multiple 4-Mbit partitions, the exact number depending on device density. By dividing the memory array into partitions, program or erase operations can take place simultaneously during read operations. Burst reads can traverse
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Datasheet
Intel(R) Wireless Flash Memory (W18)
partition boundaries, but user application code is responsible for ensuring that they don't extend into a partition that is actively programming or erasing. Although each partition has burst-read, write, and erase capabilities, simultaneous operation is limited to write or erase in one partition while other partitions are in a read mode. Augmented erase-suspend functionality further enhances the RWW capabilities of this device. An erase can be suspended to perform a program or read operation within any block, except that which is erase-suspended. A program operation nested within a suspended erase can subsequently be suspended to read yet another memory location. After device power-up or reset, the W18 device defaults to asynchronous read configuration. Writing to the device's configuration register enables synchronous burst-mode read operation. In synchronous mode, the CLK input increments an internal burst address generator. CLK also synchronizes the flash memory with the host CPU and outputs data on every, or on every other, valid CLK cycle after an initial latency. A programmable WAIT output signals to the CPU when data from the flash memory device is ready. In addition to its improved architecture and interface, the W18 device incorporates Enhanced Factory Programming (EFP), a feature that enables fast programming and low-power designs. The EFP feature provides the fastest currently-available program performance, which can increase a factory's manufacturing throughput. The device supports read operations at 1.8 V and erase and program operations at 1.8 V or 12 V. With the 1.8-V option, VCC and VPP can be tied together for a simple, ultra-low-power design. In addition to voltage flexibility, the dedicated VPP input provides complete data protection when VPP VPPLK. This device allows I/O operation at voltages even lower than the minimum VCCQ of 1.7 V. This Extended VCCQ range, 1.35 V - 1.8 V, permits even greater system design flexibility. A 128-bit protection register enhances the user's ability to implement new security techniques and data protection schemes. Unique flash device identification and fraud-, cloning-, or contentprotection schemes are possible through a combination of factory-programmed and user-OTP data cells. Zero-latency locking/unlocking on any memory block provides instant and complete protection for critical system code and data. An additional block lock-down capability provides hardware protection where software commands alone cannot change the block's protection status. The device's Command User Interface (CUI) is the system processor's link to internal flash memory operation. A valid command sequence written to the CUI initiates device Write State Machine (WSM) operation that automatically executes the algorithms, timings, and verifications necessary to manage flash memory program and erase. An internal status register provides ready/ busy indication results of the operation (success, fail, and so on). Three power-saving features- Automatic Power Savings (APS), standby, and RST#- can significantly reduce power consumption. The device automatically enters APS mode following read cycle completion. Standby mode begins when the system deselects the flash memory by de-asserting CE#. Driving RST# low produces power savings similar to standby mode. It also resets the part to read-array mode (important for system-level reset), clears internal status registers, and provides an additional level of flash write protection.
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Intel(R) Wireless Flash Memory (W18)
2.2
Package Diagram
The W18 device is available in a 56-ball VF BGA and BGA Chip SCale Package with 0.75 mm ball pitch, or the 88-ball (80 active balls) QUAD+ SCSP package. Figure 1 shows the device ballout for the VF BGA and BGA package. Figure 2 shows the device ballout for the QUAD+ package.
Figure 1. 56-Ball VF BGA / BGA Ballout
1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1
A A11 B A12 C A13 D A15 E VCCQ F VSS G DQ7 VSSQ DQ5 VCC DQ3 VCCQ DQ8 VSSQ VSSQ DQ8 VCCQ DQ3 VCC DQ5 VSSQ DQ7 DQ14 DQ13 DQ11 DQ10 DQ9 DQ0 OE# OE# DQ0 DQ9 DQ10 DQ11 DQ13 DQ14 VSS DQ15 DQ6 DQ4 DQ2 DQ1 CE# A0 A0 CE# DQ1 DQ2 DQ4 DQ6 DQ15 VCCQ A14 WAIT A16 DQ12 WP# A22 A1 A1 A22 WP# DQ12 A16 WAIT A14 A15 A10 A21 ADV# WE# A19 A7 A2 A2 A7 A19 WE# ADV# A21 A10 A13 A9 A20 CLK RST# A17 A5 A3 A3 A5 A17 RST# CLK A20 A9 A12 A8 VSS VCC VPP A18 A6 A4 A4 A6 A18 VPP VCC VSS A8 A11
A
B
C
D
E
F
G
Top View - Ball Side Down Complete Ink Mark Not Shown
Bottom View - Ball Side Up
NOTES: 1. On lower density devices, upper address balls can be treated as NC. (Example: For 32-Mbit density, A21 and A22 will be NC). 2. See Appendix C, "Mechanical Specifications" on page 95 for mechanical specifications for the package.
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Intel(R) Wireless Flash Memory (W18)
Figure 2. 88-Ball (80 Active Balls) QUAD+ Ballout
1 2 3 4 5 6 7 8
A
DU
DU
DU
DU
B
A4 A18 A19 VSS F1-VCC F2-VCC A21 A11
C
A5 R-LB# A23 VSS S-CS2 CLK A22 A12
D
A3 A17 A24 F-VPP, F-VPEN R-WE# P1-CS# A9 A13
E
A2 A7 A25 F-WP# ADV# A20 A10 A15
F
A1 A6 R-UB# F-RST# F-WE# A8 A14 A16
G
A0 D8 D2 D10 D5 D13 WAIT F2-CE#
H
R-OE# D0 D1 D3 D12 D14 D7 F2-OE#
J
S-CS1# F1-OE# D9 D11 D4 D6 D15 VCCQ
K
F1-CE# P2-CS# F3-CE# S-VCC P-VCC F2-VCC VCCQ P-Mode, P-CRE
L
VSS VSS DU VCCQ F1-VCC VSS VSS VSS DU VSS DU
M
DU
Top View - Ball Side Down Legend: Global SRAM/PSRAM specific Flash specific
NOTES: 1. Unused upper address balls can be treated as NC (for 128Mbit, A[25:23] are not used). 2. See Appendix C, "Mechanical Specifications" on page 95 for mechanical specifications for the package.
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Intel(R) Wireless Flash Memory (W18)
2.3
Signal Descriptions
Table 1 describes ball usage.
Table 1.
Symbol A[22:0] D[15:0]
Signal Descriptions
Type I I/O Name and Function ADDRESS INPUTS: For memory addresses. 32 Mbit: A[20:0]; 64 Mbit: A[21:0]; 128 Mbit: A[22:0] DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles; outputs data during memory, status register, protection register, and configuration code reads. Data pins float when the chip or outputs are deselected. Data is internally latched during writes. ADDRESS VALID: ADV# indicates valid address presence on address inputs. During synchronous read operations, all addresses are latched on ADV#'s rising edge or the next valid CLK edge with ADV# low, whichever occurs first. CHIP ENABLE: Asserting CE# activates internal control logic, I/O buffers, decoders, and sense amps. De-asserting CE# deselects the device, places it in standby mode, and tri-states all outputs. CLOCK: CLK synchronizes the device to the system bus frequency during synchronous reads and increments an internal address generator. During synchronous read operations, addresses are latched on ADV#'s rising edge or the next valid CLK edge with ADV# low, whichever occurs first. OUTPUT ENABLE: When asserted, OE# enables the device's output data buffers during a read cycle. When OE# is deasserted, data outputs are placed in a high-impedance state. RESET: When low, RST# resets internal automation and inhibits write operations. This provides data protection during power transitions. de-asserting RST# enables normal operation and places the device in asynchronous read-array mode. WAIT: The WAIT signal indicates valid data during synchronous read modes. It can be configured to be asserted-high or asserted-low based on bit 10 of the Configuration Register. WAIT is tri-stated if CE# is deasserted. WAIT is not gated by OE#. WRITE ENABLE: WE# controls writes to the CUI and array. Addresses and data are latched on the rising edge of WE#. WRITE PROTECT: Disables/enables the lock-down function. When WP# is asserted, the lock-down mechanism is enabled and blocks marked lock-down cannot be unlocked through software. See Section 7.1, "Block Lock Operations" on page 39 for details on block locking. ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming. Memory contents cannot be altered when VPP VPPLK. Block erase and program at invalid VPP voltages should not be attempted.
ADV#
I
CE#
I
CLK
I
OE#
I
RST#
I
WAIT
O
WE#
I
WP#
I
VPP
Pwr/I
Set VPP = VCC for in-system program and erase operations. To accommodate resistor or diode drops from the system supply, the VIH level of VPP can be as low as VPP1 min. VPP must remain above VPP1 min to perform in-system flash modification. VPP may be 0 V during read operations. VPP2 can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. VPP can be connected to 12 V for a cumulative total not to exceed 80 hours. Extended use of this pin at 12 V may reduce block cycling capability.
VCC VCCQ VSS
Pwr Pwr Pwr
DEVICE POWER SUPPLY: Writes are inhibited at VCC VLKO. Device operations at invalid VCC voltages should not be attempted. OUTPUT POWER SUPPLY: Enables all outputs to be driven at VCCQ. This input may be tied directly to VCC. GROUND: Pins for all internal device circuitry must be connected to system ground.
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Intel(R) Wireless Flash Memory (W18)
Table 1.
Symbol VSSQ DU NC
Signal Descriptions
Type Pwr Name and Function OUTPUT GROUND: Provides ground to all outputs which are driven by VCCQ. This signal may be tied directly to VSS. DON'T USE: Do not use this pin. This pin should not be connected to any power supplies, signals or other pins and must be floated. NO CONNECT: No internal connection; can be driven or floated.
2.4
Memory Map and Partitioning
The W18 device is divided into 4-Mbit physical partitions, which allows simultaneous RWW or RWE operations and allows users to segment code and data areas on 4-Mbit boundaries. The device's memory array is asymmetrically blocked, which enables system code and data integration within a single flash device. Each block can be erased independently in block erase mode. Simultaneous program and erase operations are not allowed; only one partition at a time can be actively programming or erasing. See Table 2, "Bottom Parameter Memory Map" on page 16 and Table 3, "Top Parameter Memory Map" on page 17. The 32-Mbit device has eight partitions, the 64-Mbit device has 16 partitions, and the 128-Mbit device has 32 partitions. Each device density contains one parameter partition and several main partitions. The 4-Mbit parameter partition contains eight 4-Kword parameter blocks and seven 32Kword main blocks. Each 4-Mbit main partition contains eight 32-Kword blocks each. The bulk of the array is divided into main blocks that can store code or data, and parameter blocks that allow storage of frequently updated small parameters that are normally stored in EEPROM. By using software techniques, the word-rewrite functionality of EEPROMs can be emulated.
.
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Intel(R) Wireless Flash Memory (W18)
Table 2.
Size (KW) Sixteen Partitions 32 .. .
Bottom Parameter Memory Map
Blk # 32 Mbit Blk # 64 Mbit Blk # 262 .. . 128 Mbit 7F8000-7FFFFF .. . 400000-407FFF 3F8000-3FFFFF .. . 200000-207FFF 1F8000-1FFFFF .. . 100000-107FFF 0F8000-0FFFFF .. . 0C0000-0C7FFF 0B8000-0BFFFF .. . 080000-087FFF 078000-07FFFF .. . 040000-047FFF 038000-03FFFF .. . 008000-00FFFF 007000-007FFF .. . 000000-000FFF
32
135
Eight Partitions
32 .. .
134 .. .
3F8000-3FFFFF .. .
134 .. . 71 70 .. . 39 38 .. . 31 30 .. . 23 22 .. . 15 14 .. . 8 7 .. . 0
32
71
200000-207FFF
Four Partitions
32 .. .
70 .. .
1F8000-1FFFFF .. .
70 .. .
1F8000-1FFFFF .. . 100000-107FFF 0F8000-0FFFFF .. . 0C0000-0C7FFF 0B8000-0BFFFF .. . 080000-087FFF 078000-07FFFF .. . 040000-047FFF 038000-03FFFF .. . 008000-00FFFF 007000-007FFF .. . 000000-000FFF
Main Partitions
32
39
100000-107FFF
39
One Partition
32 .. .
38 .. .
0F8000-0FFFFF .. .
38 .. . 31 30 .. . 23 22 .. . 15 14 .. . 8 7 .. . 0
32
31
0C0000-0C7FFF
One Partition
32 .. .
30 .. .
0B8000-0BFFFF .. . 080000-087FFF 078000-07FFFF .. . 040000-047FFF 038000-03FFFF .. . 008000-00FFFF 007000-007FFF .. . 000000-000FFF
32
23
One Partition
32 .. .
22 .. . 15 14 .. . 8 7 .. . 0
32 32 .. .
Parameter Partition
One Partition
32 4 .. . 4
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Intel(R) Wireless Flash Memory (W18)
Table 3.
Size (KW) Parameter Partition 4 .. .
Top Parameter Memory Map
Blk # 70 .. . 32 Mbit 1FF000-1FFFFF .. . Blk # 134 .. . 64 Mbit 3FF000-3FFFFF .. . Blk # 262 .. . 128 Mbit 7FF000-7FFFFF .. . 7F8000-7F8FFF 7F0000-7F7FFF .. . 7C0000-7C7FFF 7B8000-7BFFFF .. . 780000-787FFF 778000-77FFFF .. . 740000-747FFF 738000-73FFFF .. . 700000-707FFF 6F8000-6FFFFF .. . 600000-607FFF 5F8000-5FFFFF .. . 400000-407FFF 3F8000-3FFFFF .. . 000000-007FFF
One Partition
4 32 .. .
63 62 .. .
1F8000-1F8FFF 1F0000-1F7FFF .. .
127 126 .. .
3F8000-3F8FFF 3F0000-3F7FFF .. .
255 254 .. . 248 247 .. . 240 239 .. . 232 231 .. . 224 223 .. . 192 191 .. . 128 127 .. . 0
32
56
1C0000-1C7FFF
120
3C0000-3C7FFF
One Partition
32 .. .
55 .. .
1B8000-1BFFFF .. .
119 .. .
3B8000-3BFFFF .. . 380000-387FFF 378000-37FFFF .. . 340000-347FFF 338000-33FFFF .. . 300000-307FFF 2F8000-2FFFFF .. . 200000-207FFF 1F8000-1FFFFF .. . 000000-007FFF
32
48
18000-187FFF
112
One Partition
32 .. .
47 .. .
178000-17FFFF .. .
111 .. . 104 103 .. . 96 95 .. . 64 63 .. . 0
32
40
140000-147FFF
One Partition
32 .. .
39 .. .
138000-13FFFF .. . 100000-107FFF 0F8000-0FFFFF .. . 000000-007FFF
Main Partitions
32
32
Four Partitions
32 .. .
31 .. . 0
32
Eight Partitions Sixteen Partitions
32 .. . 32 32 .. . 32
Datasheet
17
Intel(R) Wireless Flash Memory (W18)
3.0
Device Operations
This section provides an overview of device operations. The 1.8 Volt Intel(R) Wireless Flash memory family includes an on-chip WSM to manage block erase and program algorithms. Its CUI allows minimal processor overhead with RAM-like interface timings.
3.1
Table 4.
Mode Reset Write Read Output Disable Standby
Bus Operations
Bus Operations
RST# VIL VIH VIH VIH VIH CE# X VIL VIL VIL VIH OE# X VIH VIL VIH X WE# X VIL VIH VIH X ADV# X VIL VIL X X WAIT High-Z Asserted Active Asserted High-Z D[15:0] High-Z DIN DOUT High-Z High-Z Notes 1,2 3 4 1 1
NOTES: 1. X = Don't Care (VIL or VIH). 2. RST# must be at VSS 0.2 V to meet the maximum specified power-down current. 3. Refer to the Table 6, "Bus Cycle Definitions" on page 23 for valid DIN during a write operation. 4. WAIT is only valid during synchronous array read operations.
3.1.1
Read
The 1.8 Volt Intel Wireless Flash memory has several read configurations:
* Asynchronous page mode read. * Synchronous burst mode read -- outputs four, eight, sixteen, or continuous words, from main
blocks and parameter blocks. Several read modes are available in each partition:
* Read-array mode: read accesses return flash array data from the addressed locations. * Read identifier mode: reads return manufacturer and device identifier data, block lock status,
and protection register data. Identifier information can be accessed starting at 4-Mbit partition base addresses; the flash array is not accessible in read identifier mode.
* Read query mode: reads return device CFI data. CFI information can be accessed starting at
4-Mbit partition base addresses; the flash array is not accessible in read query mode.
* Read status register mode: reads return status register data from the addressed partition. That
partition's array data is not accessible. A system processor can check the status register to determine an addressed partition's state or monitor program and erase progress. All partitions support the synchronous burst mode that internally sequences addresses with respect to the input CLK to select and supply data to the outputs. Identifier codes, query data, and status register read operations execute as single-synchronous or asynchronous read cycles. WAIT is asserted during these reads.
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Intel(R) Wireless Flash Memory (W18)
Access to the modes listed above is independent of VPP. An appropriate CUI command places the device in a read mode. At initial power-up or after reset, the device defaults to asynchronous readarray mode. Asserting CE# enables device read operations. The device internally decodes upper address inputs to determine which partition is accessed. Asserting ADV# opens the internal address latches. Asserting OE# activates the outputs and gates selected data onto the I/O bus. In asynchronous mode, the address is latched when ADV# is deasserted (when the device is configured to use ADV#). In synchronous mode, the address is latched by either the rising edge of ADV# or the rising (or falling) CLK edge while ADV# remains asserted, whichever occurs first. WE# and RST# must be at deasserted during read operations. Note: If only asynchronous reads are to be performed in your system, CLK should be tied to a valid VIH level, WAIT signal can be floated and ADV# must be tied to ground.
3.1.2
Burst Suspend
The Burst Suspend feature allows the system to temporarily suspend a synchronous burst operation if the system needs to use the flash address and data bus for other purposes. Burst accesses can be suspended during the initial latency (before data is received) or after the device has output data. When a burst access is suspended, internal array sensing continues and any previously latched internal data is retained. Burst Suspend occurs when CE# is asserted, the current address has been latched (either ADV# rising edge or valid CLK edge), CLK is halted, and OE# is deasserted. CLK can be halted when it is at VIH or VIL. To resume the burst access, OE# is reasserted and CLK is restarted. Subsequent CLK edges resume the burst sequence where it left off. Within the device, CE# gates WAIT. Therefore, during Burst Suspend WAIT remains asserted and does not revert to a high-impedance state when OE# is deasserted. This can cause contention with another device attempting to control the system's READY signal during a Burst Suspend. System using the Burst Suspend feature should not connect the device's WAIT signal directly to the system's READY signal. Refer to Figure 27, "Burst Suspend" on page 73.
3.1.3
Standby
De-asserting CE# deselects the device and places it in standby mode, substantially reducing device power consumption. In standby mode, outputs are placed in a high-impedance state independent of OE#. If deselected during a program or erase algorithm, the device shall consume active power until the program or erase operation completes.
3.1.4
Reset
The device enters a reset mode when RST# is asserted. In reset mode, internal circuitry is turned off and outputs are placed in a high-impedance state. After returning from reset, a time tPHQV is required until outputs are valid, and a delay (tPHWV) is required before a write sequence can be initiated. After this wake-up interval, normal operation is restored. The device defaults to read-array mode, the status register is set to 80h, and the configuration register defaults to asynchronous page-mode reads.
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19
Intel(R) Wireless Flash Memory (W18)
If RST# is asserted during an erase or program operation, the operation aborts and the memory contents at the aborted block or address are invalid. See Figure 33, "Reset Operations Waveforms" on page 80 for detailed information regarding reset timings. Like any automated device, it is important to assert RST# during system reset. When the system comes out of reset, the processor expects to read from the flash memory array. Automated flash memories provide status information when read during program or erase operations. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. 1.8 Volt Intel Flash memories allow proper CPU initialization following a system reset through the use of the RST# input. In this application, RST# is controlled by the same CPU reset signal, RESET#.
3.1.5
Write
A write occurs when CE# and WE# are asserted and OE# is deasserted. Flash control commands are written to the CUI using standard microprocessor write timings. Proper use of the ADV# input is needed for proper latching of the addresses. Refer to Section 11.3, "AC Write Characteristics" on page 74 for details. The address and data are latched on the rising edge of WE#. Write operations are asynchronous; CLK is ignored (but still may be kept active/toggling). The CUI does not occupy an addressable memory location within any partition. The system processor must access it at the correct address range depending on the kind of command executed. Programming or erasing may occur in only one partition at a time. Other partitions must be in one of the read modes or erase suspend mode. Table 5, "Command Codes and Descriptions" on page 21 shows the available commands. Appendix A, "Write State Machine States" on page 83 provides information on moving between different operating modes using CUI commands.
3.2
Device Commands
The device's on-chip WSM manages erase and program algorithms. This local CPU (WSM) controls the device's in-system read, program, and erase operations. Bus cycles to or from the flash memory conform to standard microprocessor bus cycles. RST#, CE#, OE#, WE#, and ADV# control signals dictate data flow into and out of the device. WAIT informs the CPU of valid data during burst reads. Table 4, "Bus Operations" on page 18 summarizes bus operations. Device operations are selected by writing specific commands into the device's CUI. Table 5, "Command Codes and Descriptions" on page 21 lists all possible command codes and descriptions. Table 6, "Bus Cycle Definitions" on page 23 lists command definitions. Because commands are partition-specific, it is important to issue write commands within the target address range.
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Intel(R) Wireless Flash Memory (W18)
Table 5.
Operation
Command Codes and Descriptions (Sheet 1 of 2)
Code FFh 70h Device Command Read Array Read Status Register Read Identifier Description Places selected partition in read-array mode. Places selected partition in status register read mode. The partition enters this mode after a Program or Erase command is issued to it. Puts the selected partition in read identifier mode. Device reads from partition addresses output manufacturer/device codes, configuration register data, block lock status, or protection register data on D[15:0]. Puts the addressed partition in read query mode. Device reads from the partition addresses output CFI information on D[7:0]. The WSM can set the status register's block lock (SR[1]), VPP (SR[3]), program (SR[4]), and erase (SR[5]) status bits, but it cannot clear them. SR[5:3,1] can only be cleared by a device reset or through the Clear Status Register command. This preferred program command's first cycle prepares the CUI for a program operation. The second cycle latches address and data, and executes the WSM program algorithm at this location. Status register updates occur when CE# or OE# is toggled. A Read Array command is required to read array data after programming. Equivalent to a Program Setup command (40h). This program command activates EFP mode. The first write cycle sets up the command. If the second cycle is an EFP Confirm command (D0h), subsequent writes provide program data. All other commands are ignored after EFP mode begins. If the first command was EFP Setup (30h), the CUI latches the address and data, and prepares the device for EFP mode. This command prepares the CUI for Block Erase. The device erases the block addressed by the Erase Confirm command. If the next command is not Erase Confirm, the CUI sets status register bits SR[5:4] to indicate command sequence error and places the partition in the read status register mode. If the first command was Erase Setup (20h), the CUI latches address and data, and erases the block indicated by the erase confirm cycle address. During program or erase, the partition responds only to Read Status Register, Program Suspend, and Erase Suspend commands. CE# or OE# toggle updates status register data. This command, issued at any device address, suspends the currently executing program or erase operation. Status register data indicates the operation was successfully suspended if SR[2] (program suspend) or SR[6] (erase suspend) and SR[7] are set. The WSM remains in the suspended state regardless of control signal states (except RST#). This command, issued at any device address, resumes the suspended program or erase operation. This command prepares the CUI lock configuration. If the next command is not Lock Block, Unlock Block, or Lock-Down, the CUI sets SR[5:4] to indicate command sequence error. If the previous command was Lock Setup (60h), the CUI locks the addressed block. If the previous command was Lock Setup (60h), the CUI latches the address and unlocks the addressed block. If previously locked-down, the operation has no effect. If the previous command was Lock Setup (60h), the CUI latches the address and locks-down the addressed block.
90h Read 98h
Read Query Clear Status Register
50h
40h
Word Program Setup
10h Program 30h
Alternate Setup
EFP Setup
D0h
EFP Confirm
20h Erase D0h
Erase Setup
Erase Confirm
B0h Suspend D0h
Program Suspend or Erase Suspend Suspend Resume Lock Setup
60h
01h Block Locking D0h
Lock Block
Unlock Block
2Fh
Lock-Down
Datasheet
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Intel(R) Wireless Flash Memory (W18)
Table 5.
Operation
Command Codes and Descriptions (Sheet 2 of 2)
Code Device Command Protection Program Setup Configuration Setup Set Configuration Register Description This command prepares the CUI for a protection register program operation. The second cycle latches address and data, and starts the WSM's protection register program or lock algorithm. Toggling CE# or OE# updates the flash status register data. To read array data after programming, issue a Read Array command. This command prepares the CUI for device configuration. If Set Configuration Register is not the next command, the CUI sets SR[5:4] to indicate command sequence error. If the previous command was Configuration Setup (60h), the CUI latches the address and writes the data from A[15:0] into the configuration register. Subsequent read operations access array data.
Protection
C0h
60h Configuration 03h
NOTE: Do not use unassigned commands. Intel reserves the right to redefine these codes for future functions.
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Intel(R) Wireless Flash Memory (W18)
Table 6.
Operation
Bus Cycle Definitions
Command Bus Cycles 1 2 2 2 1 2 2 >2 1 1 2 2 2 2 First Bus Cycle Oper Write Write Write Write Write Write Write Write Write Write Write Write Write Write Addr1 PnA PnA PnA PnA XX BA WA WA XX XX BA BA BA PA Data2,3 FFh 90h 98h 70h 50h 20h 40h/10h 30h B0h D0h 60h 60h 60h C0h Write Write Write Write BA BA BA PA 01h D0h 2Fh PD Write Write Write BA WA WA D0h WD D0h Second Bus Cycle Oper Read Read Read Read Addr1 Read Address PBA+IA PBA+QA PnA Data2,3 Array Data IC QD SRD
Read Array/Reset Read Identifier Read Read Query Read Status Register Clear Status Register Block Erase Program and Erase Word Program EFP Program/Erase Suspend Program/Erase Resume Lock Block Lock Unlock Block Lock-Down Block Protection Program Protection Lock Protection Program
2
Write
LPA
C0h
Write
LPA
FFFDh
Configuration
Set Configuration Register
2
Write
CD
60h
Write
CD
03h
NOTES: 1. First-cycle command addresses should be the same as the operation's target address. Examples: the first-cycle address for the Read Identifier command should be the same as the Identification code address (IA); the first-cycle address for the Word Program command should be the same as the word address (WA) to be programmed; the first-cycle address for the Erase/ Program Suspend command should be the same as the address within the block to be suspended; etc. XX = Any valid address within the device. IA = Identification code address. BA = Block Address. Any address within a specific block. LPA = Lock Protection Address is obtained from the CFI (through the Read Query command). The 1.8 Volt Intel Wireless Flash memory family's LPA is at 0080h. PA = User programmable 4-word protection address. PnA = Any address within a specific partition. PBA = Partition Base Address. The very first address of a particular partition. QA = Query code address. WA = Word address of memory location to be written. 2. SRD = Status register data. WD = Data to be written at location WA. IC = Identifier code data. PD = User programmable 4-word protection data. QD = Query code data on D[7:0]. CD = Configuration register code data presented on device addresses A[15:0]. A[MAX:16] address bits can select any partition. See Table 13, "Configuration Register Definitions" on page 47 for configuration register bits descriptions. 3. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
Datasheet
23
Intel(R) Wireless Flash Memory (W18)
3.3
Command Sequencing
When issuing a 2-cycle write sequence to the flash device, a read operation is allowed to occur between the two write cycles. The setup phase of a 2-cycle write sequence places the addressed partition into read-status mode, so if the same partition is read before the second "confirm" write cycle is issued, status register data will be returned. Reads from other partitions, however, can return actual array data assuming the addressed partition is already in read-array mode. Figure 3 on page 24 and Figure 4 on page 24 illustrate these two conditions.
Figure 3. Normal Write and Read Cycles
Address [A] WE# [W] OE# [G] Data [Q]
Partition A
Partition A
Partition A
20h
Block Erase Setup
D0h
Block Erase Conf irm
FFh
Read Array
Figure 4. Interleaving a 2-Cycle Write Sequence with an Array Read
Address [A] WE# [W] OE# [G] Data [Q]
Partition B
Partition A
Partition B
Partition A
FFh
Read Array
20h
Erase Setup
Array Data
Bus Read
D0h
Erase Conf irm
By contrast, a write bus cycle may not interrupt a 2-cycle write sequence. Doing so causes a command sequence error to appear in the status register. Figure 5 illustrates a command sequence error. Figure 5. Improper Command Sequencing
Address [A] WE# [W] OE# [G] Data [D/Q]
Partition X
Partitio n Y
Partition X
Partition X
20h
FFh
D0h
SR Data
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Intel(R) Wireless Flash Memory (W18)
4.0
4.1
Read Operations
Read Array
The Read Array command places (or resets) the partition in read-array mode and is used to read data from the flash memory array. Upon initial device power-up, or after reset (RST# transitions from VIL to VIH), all partitions default to asynchronous read-array mode. To read array data from the flash device, first write the Read Array command (FFh) to the CUI and specify the desired word address. Then read from that address. If a partition is already in read-array mode, issuing the Read Array command is not required to read from that partition. If the Read Array command is written to a partition that is erasing or programming, the device presents invalid data on the bus until the program or erase operation completes. After the program or erase finishes in that partition, valid array data can then be read. If an Erase Suspend or Program Suspend command suspends the WSM, a subsequent Read Array command places the addressed partition in read-array mode. The Read Array command functions independently of VPP.
4.2
Read Device ID
The read identifier mode outputs the manufacturer/device identifier, block lock status, protection register codes, and configuration register data. The identifier information is contained within a separate memory space on the device and can be accessed along the 4-Mbit partition address range supplied by the Read Identifier command (90h) address. Reads from addresses in Table 7 retrieve ID information. Issuing a Read Identifier command to a partition that is programming or erasing places that partition's outputs in read ID mode while the partition continues to program or erase in the background.
Table 7.
Device Identification Codes (Sheet 1 of 2)
Address1 Item Base Manufacturer ID Partition Offset 00h 0089h 8862h 8863h 8864h Device ID Partition 01h 8865h 8866h 8867h Block Lock Status(2) D0 = 0 Block 02h D0 = 1 Block Lock-Down Status(2) Configuration Register D1 = 0 Block Partition 02h D1 = 1 05h Register Data Block is locked down Block is locked Block is not locked-down 64-Mbit BPD 128-Mbit TPD 128-Mbit BPD Block is unlocked 32-Mbit TPD 32-Mbit BPD 64-Mbit TPD Data Description
Datasheet
25
Intel(R) Wireless Flash Memory (W18)
Table 7.
Device Identification Codes (Sheet 2 of 2)
Address1 Item Base Protection Register Lock Status Protection Register Partition Partition Offset 80h 81h - 88h Lock Data Register Data Multiple reads required to read the entire 128-bit Protection Register. Data Description
NOTES: 1. The address is constructed from a base address plus an offset. For example, to read the Block Lock Status for block number 38 in a BPD, set the address to the BBA (0F8000h) plus the offset (02h), i.e. 0F8002h. Then examine bit 0 of the data to determine if the block is locked. 2. See Section 7.1.4, "Block Lock Status" on page 41 for valid lock status.
4.3
Read Query (CFI)
This device contains a separate CFI query database that acts as an "on-chip datasheet." The CFI information within this device can be accessed by issuing the Read Query command and supplying a specific address. The address is constructed from the base address of a partition plus a particular offset corresponding to the desired CFI field. Appendix B, "Common Flash Interface" on page 86 shows accessible CFI fields and their address offsets. Issuing the Read Query command to a partition that is programming or erasing puts that partition in read query mode while the partition continues to program or erase in the background.
4.4
Read Status Register
The device's status register displays program and erase operation status. A partition's status can be read after writing the Read Status Register command to any location within the partition's address range. Read-status mode is the default read mode following a Program, Erase, or Lock Block command sequence. Subsequent single reads from that partition will return its status until another valid command is written. The read-status mode supports single synchronous and single asynchronous reads only; it doesn't support burst reads. The first falling edge of OE# or CE# latches and updates status register data. The operation doesn't affect other partitions' modes. Because the status register is 8 bits wide, only DQ [7:0] contains valid status register data; DQ [15:8] contains zeros. See Table 8, "Status Register Definitions" on page 27 and Table 9, "Status Register Descriptions" on page 27. Each 4-Mbit partition contains its own status register. Bits SR[6:0] are unique to each partition, but SR[7], the Device WSM Status (DWS) bit, pertains to the entire device. SR[7] provides program and erase status of the entire device. By contrast, the Partition WSM Status (PWS) bit, SR[0], provides program and erase status of the addressed partition only. Status register bits SR[6:1] present information about partition-specific program, erase, suspend, VPP, and block-lock states. Table 10, "Status Register Device WSM and Partition Write Status Description" on page 27 presents descriptions of DWS (SR[7]) and PWS (SR[0]) combinations.
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Intel(R) Wireless Flash Memory (W18)
Table 8.
DWS 7
Status Register Definitions
ESS 6 ES 5 PS 4 VPPS 3 PSS 2 DPS 1 PWS 0
Table 9.
Bit 7
Status Register Descriptions
Name DWS State 0 = Device WSM is Busy 1 = Device WSM is Ready 0 = Erase in progress/completed 1 = Erase suspended 0 = Erase successful 1 = Erase error 0 = Program successful 1 = Program error 0 = VPP OK 1 = VPP low detect, operation aborted 0 = Program in progress/completed 1 = Program suspended 0 = Unlocked 1 = Aborted erase/program attempt on locked block 0 = This partition is busy, but only if SR[7]=0 1 = Another partition is busy, but only if SR[7]=0 Description SR[7] indicates erase or program completion in the device. SR[6:1] are invalid while SR[7] = 0. See Table 10 for valid SR[7] and SR[0] combinations. After issuing an Erase Suspend command, the WSM halts and sets SR[7] and SR[6]. SR[6] remains set until the device receives an Erase Resume command. SR[5] is set if an attempted erase failed. A Command Sequence Error is indicated when SR[7,5:4] are set. SR[4] is set if the WSM failed to program a word. The WSM indicates the VPP level after program or erase completes. SR[3] does not provide continuous VPP feedback and isn't guaranteed when VPP VPP1/2. After receiving a Program Suspend command, the WSM halts execution and sets SR[7] and SR[2]. They remain set until a Resume command is received. If an erase or program operation is attempted to a locked block (if WP# = VIL), the WSM sets SR[1] and aborts the operation. Addressed partition is erasing or programming. In EFP mode, SR[0] indicates that a data-stream word has finished programming or verifying depending on the particular EFP phase. See Table 10 for valid SR[7] and SR[0] combinations.
Device WSM Status ESS Erase Suspend Status ES Erase Status PS Program Status VPPS VPP Status PSS
6
5 4
3
2
Program Suspend Status DPS Device Protect Status
1
0
PWS Partition Write Status
Table 10. Status Register Device WSM and Partition Write Status Description
DWS (SR[7]) 0 0 PWS (SR[0]) 0 1 Description The addressed partition is performing a program/erase operation. EFP: device has finished programming or verifying data, or is ready for data. A partition other than the one currently addressed is performing a program/erase operation. EFP: the device is either programming or verifying data. No program/erase operation is in progress in any partition. Erase and Program suspend bits (SR[6,2]) indicate whether other partitions are suspended. EFP: the device has exited EFP mode. 1 1 Won't occur in standard program or erase modes. EFP: this combination does not occur.
1
0
Datasheet
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Intel(R) Wireless Flash Memory (W18)
4.5
Clear Status Register
The Clear Status Register command clears the status register and leaves all partition output states unchanged. The WSM can set all status register bits and clear bits SR[7:6,2,0]. Because bits SR[5,4,3,1] indicate various error conditions, they can only be cleared by the Clear Status Register command. By allowing system software to reset these bits, several operations (such as cumulatively programming several addresses or erasing multiple blocks in sequence) can be performed before reading the status register to determine error occurrence. If an error is detected, the Status Register must be cleared before beginning another command or sequence. Device reset (RST# = VIL) also clears the status register. This command functions independently of VPP.
5.0
5.1
Program Operations
Word Program
When the Word Program command is issued, the WSM executes a sequence of internally timed events to program a word at the desired address and verify that the bits are sufficiently programmed. Programming the flash array changes specifically addressed bits to 0; 1 bits do not change the memory cell contents. Programming can occur in only one partition at a time. All other partitions must be in either a read mode or erase suspend mode. Only one partition can be in erase suspend mode at a time. The status register can be examined for program progress by reading any address within the partition that is busy programming. However, while most status register bits are partition-specific, the Device WSM Status bit, SR[7], is device-specific; that is, if the status register is read from any other partition, SR[7] indicates program status of the entire device. This permits the system CPU to monitor program progress while reading the status of other partitions. CE# or OE# toggle (during polling) updates the status register. Several commands can be issued to a partition that is programming: Read Status Register, Program Suspend, Read Identifier, and Read Query. The Read Array command can also be issued, but the read data is indeterminate. After programming completes, three status register bits can signify various possible error conditions. SR[4] indicates a program failure if set. If SR[3] is set, the WSM couldn't execute the Word Program command because VPP was outside acceptable limits. If SR[1] is set, the program was aborted because the WSM attempted to program a locked block. After the status register data is examined, clear it with the Clear Status Register command before a new command is issued. The partition remains in status register mode until another command is written to that partition. Any command can be issued after the status register indicates program completion. If CE# is deasserted while the device is programming, the devices will not enter standby mode until the program operation completes.
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Intel(R) Wireless Flash Memory (W18)
Figure 6. Word Program Flowchart
WORD PROGRAM PROCEDURE
Start Bus Command Operation Write Comments
Write 40h, Word Address Write Data Word Address
Program Data = 40h Setup Addr = Location to program (WA) Data Data = Data to program (WD) Addr = Location to program (WA) Read SRD Toggle CE# or OE# to update SRD Check SR[7] 1 = WSM ready 0 = WSM busy
Write
Read Read Status Register
No
Suspend Program Loop Suspend Program
Yes
Standby
SR[7] =
1
0
Repeat for subsequent programming operations. Full status register check can be done after each program or after a sequence of program operations.
Full Program Status Check (if desired) Program Complete
FULL PROGRAM STATUS CHECK PROCEDURE
Read Status Register Bus Command Operation Standby SR[3] =
0 1 1
Comments Check SR[3] 1 = VPP error Check SR[4] 1 = Data program error Check SR[1] 1 = Attempted program to locked block Program aborted
VPP Range Error Standby Program Error
SR[4] =
0
Standby
SR[1] =
0
1
Device Protect Error
SR[3] MUST be cleared before the WSM will allow further program attempts Only the Clear Staus Register command clears SR[4:3,1]. If an error is detected, clear the status register before attempting a program retry or other error recovery.
Program Successful
5.2
Factory Programming
The standard factory programming mode uses the same commands and algorithm as the Word Program mode (40h/10h). When VPP is at VPP1, program and erase currents are drawn through VCC. If VPP is driven by a logic signal, VPP1 must remain above the VPP1Min value to perform insystem flash modifications. When VPP is connected to a 12 V power supply, the device draws program and erase current directly from VPP. This eliminates the need for an external switching transistor to control the VPP voltage. Figure 15, "Examples of VPP Power Supply Configurations" on page 45 shows examples of flash power supply usage in various configurations.
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Intel(R) Wireless Flash Memory (W18)
The 12-V VPP mode enhances programming performance during the short time period typically found in manufacturing processes; however, it is not intended for extended use.12 V may be applied to VPP during program and erase operations as specified in Section 10.2, "Operating Conditions" on page 57. VPP may be connected to 12 V for a total of tPPH hours maximum. Stressing the device beyond these limits may cause permanent damage.
5.3
Enhanced Factory Program (EFP)
EFP substantially improves device programming performance through a number of enhancements to the conventional 12 Volt word program algorithm. EFP's more efficient WSM algorithm eliminates the traditional overhead delays of the conventional word program mode in both the host programming system and the flash device. Changes to the conventional word programming flowchart and internal WSM routine were developed because of today's beat-rate-sensitive manufacturing environments; a balance between programming speed and cycling performance was attained. The host programmer writes data to the device and checks the Status Register to determine when the data has completed programming. This modification essentially cuts write bus cycles in half. Following each internal program pulse, the WSM increments the device's address to the next physical location. Now, programming equipment can sequentially stream program data throughout an entire block without having to setup and present each new address. In combination, these enhancements reduce much of the host programmer overhead, enabling more of a data streaming approach to device programming. EFP further speeds up programming by performing internal code verification. With this, PROM programmers can rely on the device to verify that it has been programmed properly. From the device side, EFP streamlines internal overhead by eliminating the delays previously associated to switch voltages between programming and verify levels at each memory-word location. EFP consists of four phases: setup, program, verify and exit. Refer to Figure 7, "Enhanced Factory Program Flowchart" on page 33 for a detailed graphical representation of how to implement EFP.
5.3.1
EFP Requirements and Considerations
Ambient temperature: TA = 25 C 5 C VCC within specified operating range EFP Requirements VPP within specified VPP2 range Target block unlocked Block cycling below 100 erase cycles 1 RWW not supported2 EFP Considerations EFP programs one block at a time EFP cannot be suspended NOTES: 1. Recommended for optimum performance. Some degradation in performance may occur if this limit is exceeded, but the internal algorithm will continue to work properly. 2. Code or data cannot be read from another partition during EFP.
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Intel(R) Wireless Flash Memory (W18)
5.3.2
Setup
After receiving the EFP Setup (30h) and EFP Confirm (D0h) command sequence, SR[7] transitions from a 1 to a 0 indicating that the WSM is busy with EFP algorithm startup. A delay before checking SR[7] is required to allow the WSM time to perform all of its setups and checks (VPP level and block lock status). If an error is detected, status register bits SR[4], SR[3], and/or SR[1] are set and EFP operation terminates. Note: After the EFP Setup and Confirm command sequence, reads from the device automatically output status register data. Do not issue the Read Status Register command; it will be interpreted as data to program at WA0.
5.3.3
Program
After setup completion, the host programming system must check SR[0] to determine "data-stream ready" status (SR[0]=0). Each subsequent write after this is a program-data write to the flash array. Each cell within the memory word to be programmed to 0 receives one WSM pulse; additional pulses, if required, occur in the verify phase. SR[0]=1 indicates that the WSM is busy applying the program pulse. The host programmer must poll the device's status register for the "program done" state after each data-stream write. SR[0]=0 indicates that the appropriate cell(s) within the accessed memory location have received their single WSM program pulse, and that the device is now ready for the next word. Although the host may check full status for errors at any time, it is only necessary on a block basis, after EFP exit. Addresses must remain within the target block. Supplying an address outside the target block immediately terminates the program phase; the WSM then enters the EFP verify phase. The address can either hold constant or it can increment. The device compares the incoming address to that stored from the setup phase (WA0); if they match, the WSM programs the new data word at the next sequential memory location. If they differ, the WSM jumps to the new address location. The program phase concludes when the host programming system writes to a different block address, and data supplied must be FFFFh. Upon program phase completion, the device enters the EFP verify phase.
5.3.4
Verify
A high percentage of the flash bits program on the first WSM pulse. However, for those cells that do not completely program on their first attempt, EFP internal verification identifies them and applies additional pulses as required. The verify phase is identical in flow to the program phase, except that instead of programming incoming data, the WSM compares the verify-stream data to that which was previously programmed into the block. If the data compares correctly, the host programmer proceeds to the next word. If not, the host waits while the WSM applies an additional pulse(s). The host programmer must reset its initial verify-word address to the same starting location supplied during the program phase. It then reissues each data word in the same order as during the program phase. Like programming, the host may write each subsequent data word to WA0 or it may increment up through the block addresses.
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The verification phase concludes when the interfacing programmer writes to a different block address; data supplied must be FFFFh. Upon completion of the verify phase, the device enters the EFP exit phase.
5.3.5
Exit
SR[7]=1 indicates that the device has returned to normal operating conditions. A full status check should be performed at this time to ensure the entire block programmed successfully. After EFP exit, any valid CUI command can be issued.
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Figure 7. Enhanced Factory Program Flowchart
ENHANCED FACTORY PROGRAMMING PROCEDURE EFP Setup
Start
EFP Program
Read Status Register
EFP Verify
Read Status Register
EFP Exit
Read Status Register
VPP = 12V Unlock Block
SR[0]=1=N
Data Stream Ready? SR[0] =0=Y Write Data Address = WA0
SR[0]=1=N Verify Stream Ready? SR[0] =0=Y Write Data Address = WA0
SR[7]=0=N
EFP Exited? SR[7]=1=Y
Write 30h Address = WA0
Full Status Check Procedure
Write D0h Address = WA0 SR[0]=1=N
EFP setup time
SR[7]=0=Y
Read Status Register
Program Done? SR[0]=0=Y
SR[0]=1=N
Read Status Register
Read Status Register
Operation Complete
Verify Done? SR[0]=0=Y
N
EFP Setup Done? SR[7]=1=N Check VPP & Lock errors (SR[3,1])
Last Data? Y Write FFFFh Address BBA
N
Last Data? Y Write FFFFh Address BBA
Exit
EFP Setup
Bus State Write Write Write Standby Read Standby EFP Setup Done? Unlock Block EFP Setup Comments VPP = 12V Unlock block Data = 30h Address = WA0 Bus State Read Standby Write (note 1) Read
EFP Program
Comments Status Register Data Check SR[0] Stream 0 = Ready for data Ready? 1 = Not ready for data Data = Data to program Address = WA0 Status Register Bus State Read Standby Write (note 2) Read Standby (note 3) Standby
EFP Verify
Comments Status Register Verify Check SR[0] Stream 0 = Ready for verify Ready? 1 = Not ready for verify Data = Word to verify Address = WA0 Status Register Verify Done? Last Data? Exit Verify Phase Check SR[0] 0 = Verify done 1 = Verify not done Device automatically increments address. Data = FFFFh Address not within same BBA Status Register Check SR[7] EFP 0 = Exit not finished Exited? 1 = Exit completed
EFP Data = D0h Confirm Address = WA0 EFP setup time Status Register Check SR[7] 0 = EFP ready 1 = EFP not ready
Check SR[0] Program Standby 0 = Program done Done? 1 = Program not done Standby Last Data? Device automatically increments address.
If SR[7] = 1: Error Check SR[3,1] Standby Condition SR[3] = 1 = VPP error Check SR[1] = 1 = locked block
Write
Exit Data = FFFFh Program Address not within same Phase BBA
Write
EFP Exit
1. WA0 = first Word Address to be programmed within the target block. The BBA (Block Base Address) must remain constant throughout the program phase data stream; WA can be held constant at the first address location, or it can be written to sequence up through the addresses within the block. Writing to a BBA not equal to that of the block currently being written to terminates the EFP program phase, and instructs the device to enter the EFP verify phase. 2. For proper verification to occur , the verify data stream must be presented to the device in the same sequence as that of the program phase data stream. Writing to a BBA not equal to WA terminates the EFP verify phase, and instructs the device to exit EFP . 3. Bits that did not fully program with the single WSM pulse of the EFP program phase receive additional program-pulse attempts during the EFP verify phase. The device will report any program failure by setting SR[4]=1; this check can be performed during the full status check after EFP has been exited for that block, and will indicate any error within the entire data stream. Read Standby
Repeat for subsequent operations. After EFP exit, a Full Status Check can determine if any program error occurred. See the Full Status Check procedure in the Word Program flowchart.
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6.0
6.1
Program and Erase Operations
Program/Erase Suspend and Resume
The Program Suspend and Erase Suspend commands halt an in-progress program or erase operation. The command can be issued at any device address. The partition corresponding to the command's address remains in its previous state. A suspend command allows data to be accessed from memory locations other than the one being programmed or the block being erased. A program operation can be suspended only to perform a read operation. An erase operation can be suspended to perform either a program or a read operation within any block, except the block that is erase suspended. A program command nested within a suspended erase can subsequently be suspended to read yet another location. Once a program or erase process starts, the Suspend command requests that the WSM suspend the program or erase sequence at predetermined points in the algorithm. The partition that is actually suspended continues to output status register data after the Suspend command is written. An operation is suspended when status bits SR[7] and SR[6] and/or SR[2] are set. To read data from blocks within the partition (other than an erase-suspended block), you can write a Read Array command. Block erase cannot resume until the program operations initiated during erase suspend are complete. Read Array, Read Status Register, Read Identifier (ID), Read Query, and Program Resume are valid commands during Program or Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend, Erase Resume, Lock Block, Unlock Block, and LockDown Block are valid commands during erase suspend. To read data from a block in a partition that is not programming or erasing, the operation does not need to be suspended. If the other partition is already in read array, ID, or Query mode, issuing a valid address returns corresponding data. If the other partition is not in a read mode, one of the read commands must be issued to the partition before data can be read. During a suspend, CE# = VIH places the device in standby state, which reduces active current. VPP must remain at its program level and WP# must remain unchanged while in suspend mode. A resume command instructs the WSM to continue programming or erasing and clears status register bits SR[2] (or SR[6]) and SR[7]. The Resume command can be written to any partition. When read at the partition that is programming or erasing, the device outputs data corresponding to the partition's last mode. If status register error bits are set, the status register can be cleared before issuing the next instruction. RST# must remain at VIH. See Figure 8, "Program Suspend / Resume Flowchart" on page 35, and Figure 9, "Erase Suspend / Resume Flowchart" on page 36. If a suspended partition was placed in read array, read status register, read identifier (ID), or read query mode during the suspend, the device remains in that mode and outputs data corresponding to that mode after the program or erase operation is resumed. After resuming a suspended operation, issue the read command appropriate to the read operation. To read status after resuming a suspended operation, issue a Read Status Register command (70h) to return the suspended partition to status mode.
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Figure 8. Program Suspend / Resume Flowchart
PROGRAM SUSPEND / RESUME PROCEDURE
Start
Program Suspend
Bus Command Operation Write
Comments
Write B0h Any Address
Read Status
Program Data = B0h Suspend Addr = Block to suspend (BA) Read Status Data = 70h Addr = Same partition Status register data Toggle CE# or OE# to update Status register Addr = Suspended block (BA) Check SR.7 1 = WSM ready 0 = WSM busy Check SR.2 1 = Program suspended 0 = Program completed Read Array Data = FFh Addr = Any address within the suspended partition Read array data from block other than the one being programmed Program Data = D0h Resume Addr = Suspended block (BA)
Write
Write 70h Same Partition Read Status Register Read
SR.7 =
1
0
Standby
SR.2 =
1 Read Array
0
Program Completed
Standby
Write
Write FFh Susp Partition Read Read Array Data
Write
No
Done Reading
Yes Program Resume
If the suspended partition was placed in Read Array mode: Write
Read Array
Read Status
Return partition to Status mode: Data = 70h Addr = Same partition
Write D0h Any Address Program Resumed
Read Status
Write FFh Pgm'd Partition Read Array Data
Write 70h Same Partition
PGM_SUS.WMF
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Figure 9. Erase Suspend / Resume Flowchart
ERASE SUSPEND / RESUME PROCEDURE
Start
Erase Suspend
Bus Command Operation Write
Comments
Write B0h Any Address
Read Status
Erase Data = B0h Suspend Addr = Any address Read Status Data = 70h Addr = Same partition Status register data. Toggle CE# or OE# to update Status register Addr = Same partition Check SR.7 1 = WSM ready 0 = WSM busy Check SR.6 1 = Erase suspended 0 = Erase completed Read Array Data = FFh or 40h or Program Addr = Block to program or read Read array or program data from/to block other than the one being erased Program Data = D0h Resume Addr = Any address If the suspended partition was placed in Read Array mode or a Program Loop:
Write
Write 70h Same Partition Read Read Status Register Standby SR.7 =
1 0 0
Standby Erase Completed Write Read or Write Write
SR.6 =
1
Read
Read or Program?
No
Program
Read Array Data
Program Loop
Done?
Erase Yes Resume Read Array
Write D0h Any Address
Write FFh Erased Partition Read Array Data
Write
Read Status
Return partition to Status mode: Data = 70h Addr = Same partition
Erase Resumed
Read Status
Write 70h Same Partition
ERAS_SUS.WMF
6.2
Block Erase
The 2-cycle block erase command sequence, consisting of Erase Setup (20h) and Erase Confirm (D0h), initiates one block erase at the addressed block. Only one partition can be in an erase mode at a time; other partitions must be in a read mode. The Erase Confirm command internally latches the address of the block to be erased. Erase forces all bits within the block to 1. SR[7] is cleared while the erase executes.
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After writing the Erase Confirm command, the selected partition is placed in read status register mode and reads performed to that partition return the current status data. The address given during the Erase Confirm command does not need to be the same address used in the Erase Setup command. So, if the Erase Confirm command is given to partition B, then the selected block in partition B will be erased even if the Erase Setup command was to partition A. The 2-cycle erase sequence cannot be interrupted with a bus write operation. For example, an Erase Setup command must be immediately followed by the Erase Confirm command in order to execute properly. If a different command is issued between the setup and confirm commands, the partition is placed in read-status mode, the status register signals a command sequence error, and all subsequent erase commands to that partition are ignored until the status register is cleared. The CPU can detect block erase completion by analyzing SR[7] of that partition. If an error bit (SR[5,3,1]) was flagged, the status register can be cleared by issuing the Clear Status Register command before attempting the next operation. The partition remains in read-status mode until another command is written to its CUI. Any CUI instruction can follow after erasing completes. The CUI can be set to read-array mode to prevent inadvertent status register reads.
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Figure 10. Block Erase Flowchart
BLOCK ERASE PROCEDURE
Start Bus Command Comments Operation Block Data = 20h Write Erase Addr = Block to be erased (BA) Setup Write Write D0h and Block Address Read Read Status Register
No
Write 20h Block Address
Erase Confirm
Data = D0h Addr = Block to be erased (BA) Read SRD Toggle CE# or OE# to update SRD Check SR[7] 1 = WSM ready 0 = WSM busy
Suspend Erase Loop Suspend Erase
Standby
SR[7] =
1
0
Yes
Repeat for subsequent block erasures. Full status register check can be done after each block erase or after a sequence of block erasures.
Full Erase Status Check (if desired) Block Erase Complete
FULL ERASE STATUS CHECK PROCEDURE
Read Status Register VPP Range Error Standby
1
Bus Command Operation Standby Check SR[3] 1 = VPP error
Comments
SR[3] =
0
1
Check SR[5:4] Both 1 = Command sequence error Check SR[5] 1 = Block erase error Check SR[1] 1 = Attempted erase of locked block Erase aborted
SR[5:4] =
0
Command Sequence Error Block Erase Error Erase of Locked Block Aborted
Standby
SR[5] =
0
1
Standby
SR[1] =
0
1
SR[3,1] must be cleared before the WSM will allow further erase attempts. Only the Clear Status Register command clears SR[5:3,1]. If an error is detected, clear the Status register before attempting an erase retry or other error recovery.
Block Erase Successful
6.3
Read-While-Write and Read-While-Erase
The 1.8 Volt Intel(R) Wireless Flash memory supports flexible multi-partition dual-operation architecture. By dividing the flash memory into many separate partitions, the device can read from one partition while programing or erasing in another partition; hence the terms, RWW and RWE. Both of these features greatly enhance data storage performance.
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The product does not support simultaneous program and erase operations. Attempting to perform operations such as these results in a command sequence error. Only one partition can be programming or erasing while another partition is reading. However, one partition may be in erase suspend mode while a second partition is performing a program operation, and yet another partition is executing a read command. Table 5, "Command Codes and Descriptions" on page 21 describes the command codes available for all functions.
7.0
Security Modes
The 1.8 Volt Intel Wireless Flash memory offers both hardware and software security features to protect the flash data. The software security feature is used by executing the Lock Block command. The hardware security feature is used by executing the Lock-Down Block command and by asserting the WP# signal. Refer to Figure 11, "Block Locking State Diagram" on page 40 for a state diagram of the flash security features. Also see Figure 12, "Locking Operations Flowchart" on page 42.
7.1
Block Lock Operations
Individual instant block locking protects code and data by allowing any block to be locked or unlocked with no latency. This locking scheme offers two levels of protection. The first allows software-only control of block locking (useful for frequently changed data blocks), while the second requires hardware interaction before locking can be changed (protects infrequently changed code blocks). The following sections discuss the locking system operation. The term "state [abc]" specifies locking states; for example, "state [001]," where a = WP# value, b = block lock-down status bit D1, and c = Block Lock status register bit D0. Figure 11, "Block Locking State Diagram" on page 40 defines possible locking states. The following summarizes the locking functionality.
* All blocks power-up in a locked state. * Unlock commands can unlock these blocks, and lock commands can lock them again. * The Lock-Down command locks a block and prevents it from being unlocked when WP# is
asserted. -- Locked-down blocks can be unlocked or locked with commands as long as WP# is deasserted -- The lock-down status bit is cleared only when the device is reset or powered-down.
Block lock registers are not affected by the VPP level. They may be modified and read even if VPP VPPLK. Each block's locking status can be set to locked, unlocked, and lock-down, as described in the following sections. See Figure 12, "Locking Operations Flowchart" on page 42.
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Figure 11. Block Locking State Diagram
Power-Up/Reset
Locked [X01]
LockedDown4,5 [011]
Hardware Locked5 [011]
WP# Hardware Control
Unlocked [X00]
Software Locked [111]
Unlocked [110]
Software Block Lock (0x60/0x01) or Software Block Unlock (0x60/0xD0) Software Block Lock-Down (0x60/0x2F) WP# hardware control
Notes:
1. [a,b,c] represents [WP#, D1, D0]. X = Don't Care. 2. D1 indicates block Lock-down status. D1 = `0', Lock-down has not been issued to this block. D1 = `1', Lock-down has been issued to this block. 3. D0 indicates block lock status. D0 = `0', block is unlocked. D0 = `1', block is locked. 4. Locked-down = Hardware + Software locked. 5. [011] states should be tracked by system software to determine difference between Hardware Locked and Locked-Down states.
7.1.1
Lock
All blocks default to locked (state [x01]) after initial power-up or reset. Locked blocks are fully protected from alteration. Attempted program or erase operations to a locked block will return an error in SR[1]. Unlocked blocks can be locked by using the Lock Block command sequence. Similarly, a locked block's status can be changed to unlocked or lock-down using the appropriate software commands.
7.1.2
Unlock
Unlocked blocks (states [x00] and [110]) can be programmed or erased. All unlocked blocks return to the locked state when the device is reset or powered-down. An unlocked block's status can be changed to the locked or locked-down state using the appropriate software commands. A locked block can be unlocked by writing the Unlock Block command sequence if the block is not lockeddown.
7.1.3
Lock-Down
Locked-down blocks (state [011]) offer the user an additional level of write protection beyond that of a regular locked block. A block that is locked-down cannot have it's state changed by software if WP# is asserted. A locked or unlocked block can be locked-down by writing the Lock-Down Block command sequence. If a block was set to locked-down, then later changed to unlocked, a Lock-
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Down command should be issued prior asserting WP# will put that block back to the locked-down state. When WP# is deasserted, locked-down blocks are changed to the locked state and can then be unlocked by the Unlock Block command.
7.1.4
Block Lock Status
Every block's lock status can be read in read identifier mode. To enter this mode, issue the Read Identifier command to the device. Subsequent reads at Block Base Address + 02h will output that block's lock status. For example, to read the block lock status of block 10, the address sent to the device should be 50002h (for a top-parameter device). The lowest two data bits of the read data, D1 and D0, represent the lock status. D0 indicates the block lock status. It is set by the Lock Block command and cleared by the Block Unlock command. It is also set when entering the lock-down state. D1 indicates lock-down status and is set by the Lock-Down command. The lock-down status bit cannot be cleared by software-only by device reset or power-down. See Table 11.
Table 11. Write Protection Truth Table
VPP X VIL X X WP# X X VIL VIH RST# VIL VIH VIH VIH Write Protection Device inaccessible Word program and block erase prohibited All lock-down blocks locked All lock-down blocks can be unlocked
7.1.5
Lock During Erase Suspend
Block lock configurations can be performed during an erase suspend operation by using the standard locking command sequences to unlock, lock, or lock-down a block. This feature is useful when another block requires immediate updating. To change block locking during an erase operation, first write the Erase Suspend command. After checking SR[6] to determine the erase operation has suspended, write the desired lock command sequence to a block; the lock status will be changed. After completing lock, unlock, read, or program operations, resume the erase operation with the Erase Resume command (D0h). If a block is locked or locked-down during a suspended erase of the same block, the locking status bits change immediately. When the erase operation is resumed, it will complete normally. Locking operations cannot occur during program suspend. Appendix A, "Write State Machine States" on page 83 shows valid commands during erase suspend.
7.1.6
Status Register Error Checking
Using nested locking or program command sequences during erase suspend can introduce ambiguity into status register results. Because locking changes require 2-cycle command sequences, for example, 60h followed by 01h to lock a block, following the Configuration Setup command (60h) with an invalid command produces a command sequence error (SR[5:4]=11b). If a Lock Block command error occurs during erase suspend, the device sets SR[4] and SR[5] to 1 even after the erase is resumed. When erase is
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complete, possible errors during the erase cannot be detected from the status register because of the previous locking command error. A similar situation occurs if a program operation error is nested within an erase suspend.
7.1.7
WP# Lock-Down Control
The Write Protect signal, WP#, adds an additional layer of block security. WP# only affects blocks that once had the Lock-Down command written to them. After the lock-down status bit is set for a block, asserting WP# forces that block into the lock-down state [011] and prevents it from being unlocked. After WP# is deasserted, the block's state reverts to locked [111] and software commands can then unlock the block (for erase or program operations) and subsequently re-lock it. Only device reset or power-down can clear the lock-down status bit and render WP# ineffective.
Figure 12. Locking Operations Flowchart
LOCKING OPERATIONS PROCEDURE
Start Bus Command Operation Write 60h Block Address Write 01,D0,2Fh Block Address Write 90h BBA + 02h Optional Read Block Lock Status Write Lock Setup Comments Data = 60h Addr = Block to lock/unlock/lock-down (BA)
Write
Lock, Data = 01h (Lock block) Unlock, or D0h (Unlock block) Lockdown 2Fh (Lockdown block) Confirm Addr = Block to lock/unlock/lock-down (BA) Read ID Plane Data = 90h Addr = BBA + 02h
Write (Optional)
Read Block Lock Block Lock status data (Optional) Status Addr = BBA + 02h
No
Locking Change?
Yes
Standby (Optional) Read Array
Confirm locking change on DQ[1:0]. (See Block Locking State Transitions Table for valid combinations.) Data = FFh Addr = Any address in same partition
Write FFh Partition Address Lock Change Complete
Write
7.2
Protection Register
The 1.8 Volt Intel Wireless Flash memory includes a 128-bit protection register. This protection register is used to increase system security and for identification purposes. The protection register value can match the flash component to the system's CPU or ASIC to prevent device substitution. The lower 64 bits within the protection register are programmed by Intel with a unique number in each flash device. The upper 64 OTP bits within the protection register are left for the customer to program. Once programmed, the customer segment can be locked to prevent further programming.
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Note:
The individual bits of the user segment of the protection register are OTP, not the register in total. The user may program each OTP bit individually, one at a time, if desired. After the protection register is locked, however, the entire user segment is locked and no more user bits can be programmed. The protection register shares some of the same internal flash resources as the parameter partition. Therefore, RWW is only allowed between the protection register and main partitions. Table 12 describes the operations allowed in the protection register, parameter partition, and main partition during RWW and RWE.
Table 12. Simultaneous Operations Allowed with the Protection Register
Protection Register Parameter Partition Array Data See Description Main Partitions Description While programming or erasing in a main partition, the protection register can be read from any other partition. Reading the parameter partition data is not allowed if the protection register is being read from addresses within the parameter partition. While programming or erasing in a main partition, read operations are allowed in the parameter partition. Accessing the protection registers from parameter partition addresses is not allowed. While programming or erasing in a main partition, read operations are allowed in the parameter partition. Accessing the protection registers in a partition that is different from the one being programmed or erased, and also different from the parameter partition, is allowed. While programming the protection register, reads are only allowed in the other main partitions. Access to the parameter partition is not allowed. This is because programming of the protection register can only occur in the parameter partition, so it will exist in status mode. While programming or erasing the parameter partition, reads of the protection registers are not allowed in any partition. Reads in other main partitions are supported.
Read
Write/Erase
See Description
Read
Write/Erase
Read
Read
Write/Erase
Write
No Access Allowed
Read
No Access Allowed
Write/Erase
Read
7.2.1
Reading the Protection Register
Writing the Read Identifier command allows the protection register data to be read 16 bits at a time from addresses shown in Table 7, "Device Identification Codes" on page 25. The protection register is read from the Read Identifier command and can be read in any partition.Writing the Read Array command returns the device to read-array mode.
7.2.2
Programing the Protection Register
The Protection Program command should be issued only at the parameter (top or bottom) partition followed by the data to be programmed at the specified location. It programs the upper 64 bits of the protection register 16 bits at a time. Table 7, "Device Identification Codes" on page 25 shows allowable addresses. See also Figure 13, "Protection Register Programming Flowchart" on page 44. Issuing a Protection Program command outside the register's address space results in a status register error (SR[4]=1).
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7.2.3
Locking the Protection Register
PR-LK.0 is programmed to 0 by Intel to protect the unique device number. PR-LK.1 can be programmed by the user to lock the user portion (upper 64 bits) of the protection register (See Figure 14, "Protection Register Locking). This bit is set using the Protection Program command to program "FFFDh" into PR-LK. After PR-LK register bits are programmed (locked), the protection register's stored values can't be changed. Protection Program commands written to a locked section result in a status register error (SR[4]=1, SR[5]=1).
Figure 13. Protection Register Programming Flowchart
PROTECTION REGISTER PROGRAMMINGPROCEDURE
Start Bus Command Comments Operation Protection Data = C0h Program Write Addr = Protection address Setup Write Write Protect. Register Address / Data Read Status Register Protection Data = Data to program Program Addr = Protection address Read SRD Toggle CE# or OE# to update SRD Check SR[7] 1 = WSM Ready 0 = WSM Busy
Write C0h Addr=Prot addr
Read
Standby
SR[7] = 1?
Yes
No
Protection Program operations addresses must be within the protection register address space. Addresses outside this space will return an error. Repeat for subsequent programming operations. Full status register check can be done after each program or after a sequence of program operations.
Full Status Check (if desired) Program Complete
FULL STATUS CHECK PROCEDURE
Read SRD Bus Command Operation Standby SR[4:3] =
1,1
Comments SR[1] SR[3] SR[4] 0 1 1 VPP Error 0 0 1 Protection register program error Register locked; Operation aborted
VPP Range Error Standby
SR[4,1] =
1,0
Programming Error
Standby
1
0
1
SR[4,1] =
1,1
Locked-Register Program Aborted
SR[3] MUST be cleared before the WSM will allow further program attempts. Only the Clear Staus Register command clears SR[4:3,1]. If an error is detected, clear the status register before attempting a program retry or other error recovery.
Program Successful
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Figure 14. Protection Register Locking
0x88 User-Programmable 0x85 0x84 Intel Factory-Programmed 0x81 PR Lock Register 0 0x80
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
7.3
VPP Protection
The 1.8 Volt Intel(R) Wireless Flash memory provides in-system program and erase at VPP1. For factory programming, it also includes a low-cost, backward-compatible 12 V programming feature.(See "Factory Programming" on page 29.) The EFP feature can also be used to greatly improve factory program performance as explained in Section 5.3, "Enhanced Factory Program (EFP)" on page 30. In addition to the flexible block locking, holding the VPP programming voltage low can provide absolute hardware write protection of all flash-device blocks. If VPP is below VPPLK, program or erase operations result in an error displayed in SR[3]. (See Figure 15.)
Figure 15. Examples of VPP Power Supply Configurations
System supply 12 V supply
10K
VCC VPP
System supply Prot# (logic signal)
VCC VPP
* 12 V fast programming * Absolute write protection with V PP VPPLK
* Low-voltage programming * Absolute write protection via logic signal
System supply (Note 1) 12 V supply
VCC VPP
System supply
VCC VPP
* Low voltage and 12 V fast programming
* Low-voltage programming
NOTE: If the VCC supply can sink adequate current, you can use an appropriately valued resistor.
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8.0
Set Configuration Register
The Set Configuration Register command sets the burst order, frequency configuration, burst length, and other parameters. A two-bus cycle command sequence initiates this operation. The configuration register data is placed on the lower 16 bits of the address bus (A[15:0]) during both bus cycles. The Set Configuration Register command is written along with the configuration data (on the address bus). This is followed by a second write that confirms the operation and again presents the configuration register data on the address bus. The configuration register data is latched on the rising edge of ADV#, CE#, or WE# (whichever occurs first). This command functions independently of the applied VPP voltage. After executing this command, the device returns to read-array mode. The configuration register's contents can be examined by writing the Read Identifier command and then reading location 05h. (See Table 13 and Table 14.)
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Intel(R) Wireless Flash Memory (W18)
Table 13. Configuration Register Definitions
Read Mode Res'd First Access Latency Count WAIT Polarity Data Output Config WAIT Config Burst Seq Clock Config Res'd Res'd Burst Wrap Burst Length
RM 15
R 14
LC2 13
LC1 12
LC0 11
WT 10
DOC 9
WC 8
BS 7
CC 6
R 5
R 4
BW 3
BL2 2
BL1 1
BL0 0
Table 14. Configuration Register Descriptions
Bit Name RM Read Mode R LC2-0 Description Notes1
15 14 13-11
0 = Synchronous Burst Reads Enabled 1 = Asynchronous Reads Enabled (Default) Reserved 001 = Reserved 010 = Code 2 011 = Code 3 100 = Code 4 101 = Code 5 111 = Reserved (Default)
2 5 6
First Access Latency Count
WT
10 9 8 7
WAIT Signal Polarity
DOC
0 = WAIT signal is asserted low 1 = WAIT signal is asserted high (Default) 0 = Hold Data for One Clock 1 = Hold Data for Two Clock (Default) 0 = WAIT Asserted During Delay 1 = WAIT Asserted One Data Cycle before Delay (Default) 1 = Linear Burst Order (Default) 0 = Burst Starts and Data Output on Falling Clock Edge 1 = Burst Starts and Data Output on Rising Clock Edge (Default) Reserved Reserved 0 = Wrap bursts within burst length set by CR[2:0] 1 = Don't wrap accesses within burst length set by CR[2:0].(Default) 001 = 4-Word Burst 010 = 8-Word Burst 011 = 16-Word Burst 111 = Continuous Burst (Default)
3 6 6
Data Output Configuration
WC
WAIT Configuration
BS
Burst Sequence
CC
6 5 4 3
Clock Configuration
R R BW Burst Wrap BL2-0 Burst Length
5 5
2-0
4
NOTES: 1. Undocumented combinations of bits are reserved by Intel for future implementations. 2. Synchronous and page read mode configurations affect reads from main blocks and parameter blocks. Status register and configuration reads support single read cycles. CR[15]=1 disables configuration set by CR[14:0]. 3. Data is not ready when WAIT is asserted. 4. Set the synchronous burst length. In asynchronous page mode, the page size equals four words. 5. Set all reserved configuration register bits to zero. 6. Setting the configuration register for synchronous burst-mode with a latency count of 2 (RCR[13:11] = 010), data hold for 2 clocks (RCR.9 = 1), and WAIT asserted one data cycle before delay (RCR.8 =1) is not supported.
Datasheet
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Intel(R) Wireless Flash Memory (W18)
8.1
Read Mode (CR[15])
All partitions support two high-performance read configurations: synchronous burst mode and asynchronous page mode (default). CR[15] sets the read configuration to one of these modes. Status register, query, and identifier modes support only asynchronous and single-synchronous read operations.
8.2
First Access Latency Count (CR[13:11])
The First Access Latency Count (CR[13:11]) configuration tells the device how many clocks must elapse from ADV# de-assertion (VIH) before the first data word should be driven onto its data pins. The input clock frequency determines this value. See Table 13, "Configuration Register Definitions" on page 47 for latency values. Figure 16 shows data output latency from ADV# assertion for different latencies. Refer to Section 8.2.1, "Latency Count Settings" on page 49 for Latency Code Settings.
Figure 16. First Access Latency Configuration
CLK [C]
Valid Address
Address [A]
ADV# [V] D[15:0] [Q] Code 2
Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output
D[15:0] [Q]
Code 3
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
D[15:0] [Q]
Code 4
Valid Output
Valid Output
Valid Output
Valid Output
D[15:0] [Q]
Code 5
Valid Output
Valid Output
Valid Output
NOTE: Other First Access Latency Configuration settings are reserved.
)
Figure 17. Word Boundary
Word 0 - 3
Word 4 - 7
Word 8 - B
Word C - F
0
1
2
3
4
5
6
7
8
9
ABCDE
F
16 Word Boundary 4 Word Boundary
The 16-word boundary is the end of the device sense word-line.
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Intel(R) Wireless Flash Memory (W18)
8.2.1
Latency Count Settings
Table 15. Latency Count Settings for VCCQ = 1.35 V - 1.8 V (.13 m lithography)
VCCQ = 1.35 V - 1.8 V Unit
tAVQV/tCHQV (65ns/14ns)
Latency Count Settings Frequency
tAVQV/tCHQV (85ns/20ns) 2 < 30 3, 4, 5 < 40 MHz
2 < 39
3, 4, 5 < 54
Table 16. Latency Count Setting for VCCQ = 1.7 V - 2.24 V (.13 m lithography)
VCCQ = 1.7 - 2.24 V Unit
tAVQV/tCHQV (60ns/11ns)
Latency Count Settings Frequency Support
tAVQV/tCHQV (80ns/14ns) 2 < 30 3 < 45 4, 5 < 54 MHz
2 < 40
3 < 61
4, 5 < 66
Table 17. Latency Count Setting for VCCQ = 1.7 V - 2.24 V (.18 m lithography)
VCCQ = 1.7 - 2.24 V Unit
tAVQV/tCHQV (70ns/14ns)
Latency Count Settings Frequency Support
tAVQV/tCHQV (85ns/18ns) 2 < 29 3, 4, 5 < 40 MHz
2 < 35
3, 4, 5 <52
Datasheet
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Intel(R) Wireless Flash Memory (W18)
Figure 18. Example: Latency Count Setting at 3
tADD-DELAY CLK (C) CE# (E) ADV# (V)
0st 1nd 2rd 3th
tDATA
4th
AMAX-0 (A) Code 3 DQ15-0 (D/Q)
Valid Address
High Z
Valid Output
Valid Output
R103
8.3
WAIT Signal Polarity (CR[10])
If the WT bit is cleared (CR[10]=0), then WAIT is configured to be asserted low. This means that a 0 on the WAIT signal indicates that data is not ready and the data bus contains invalid data. Conversely, if CR[10] is set, then WAIT is asserted high. In either case, if WAIT is deasserted, then data is ready and valid. WAIT is asserted during asynchronous page mode reads.
8.4
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode (CR[15]=0), and when addressing a partition that is currently in read-array mode. The WAIT signal is only "deasserted" when data is valid on the bus. When the device is operating in synchronous non-read-array mode, such as read status, read ID, or read query, WAIT is set to an "asserted" state as determined by CR[10]. See Figure 26, "WAIT Signal in Synchronous Non-Read Array Operation Waveform" on page 72. When the device is operating in asynchronous page mode or asynchronous single word read mode, WAIT is set to an "asserted" state as determined by CR[10]. See Figure 22, "Page-Mode Read Operation Waveform" on page 68, and Figure 20, "Asynchronous Read Operation Waveform" on page 66. From a system perspective, the WAIT signal is in the asserted state (based on CR[10]) when the device is operating in synchronous non-read-array mode (such as Read ID, Read Query, or Read Status), or if the device is operating in asynchronous mode (CR[15]=1). In these cases, the system software should ignore (mask) the WAIT signal, because it does not convey any useful information about the validity of what is appearing on the data bus.
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Intel(R) Wireless Flash Memory (W18)
Table 18. WAIT Signal Conditions
CONDITION WAIT
CE# = VIH CE# = VIL OE# Synchronous Array Read Synchronous Non-Array Read All Asynchronous Read and all Write
Tri-State Active No-Effect Active Asserted Asserted
8.5
Data Hold (CR[9])
The Data Output Configuration bit (CR[9]) determines whether a data word remains valid on the data bus for one or two clock cycles. The processor's minimum data set-up time and the flash memory's clock-to-data output delay determine whether one or two clocks are needed. A Data Output Configuration set at 1-clock data hold corresponds to a 1-clock data cycle; a Data Output Configuration set at 2-clock data hold corresponds to a 2-clock data cycle. The setting of this configuration bit depends on the system and CPU characteristics. For clarification, see Figure 19, "Data Output Configuration with WAIT Signal Delay" on page 52. A method for determining this configuration setting is shown below. To set the device at 1-clock data hold for subsequent reads, the following condition must be satisfied:
t CHQV (ns) + tDATA (ns) One CLK Period (ns)
As an example, use a clock frequency of 66 MHz and a clock period of 15 ns. Assume the data output hold time is one clock. Apply this data to the formula above for the subsequent reads:
11 ns + 4 ns 15 ns
This equation is satisfied, and data output will be available and valid at every clock period. If tDATA
is long, hold for two cycles.
During page-mode reads, the initial access time can be determined by the formula:
t ADD-DELAY (ns) + tDATA (ns) + tAVQV (ns)
Subsequent reads in page mode are defined by:
t APA (ns) + tDATA (ns) (minimum time)
Datasheet
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Intel(R) Wireless Flash Memory (W18)
Figure 19. Data Output Configuration with WAIT Signal Delay
CLK [C]
WAIT (CR.8 = 1) tCHQV WAIT (CR.8 = 0) Note 1
Valid Output Valid Output Valid Output
Note 1
1 CLK Data Hold
DQ15-0 [Q]
tCHTL/H
WAIT (CR.8 = 0) WAIT (CR.8 = 1)
Note 1 tCHQV Note 1
Valid Output Valid Output
2 CLK Data Hold
DQ15-0 [Q]
NOTE: WAIT shown asserted high (CR[10]=1).
8.6
WAIT Delay (CR[8])
The WAIT configuration bit (CR[8]) controls WAIT signal delay behavior for all synchronous read-array modes. Its setting depends on the system and CPU characteristics. The WAIT can be asserted either during, or one data cycle before, a valid output. In synchronous linear read array (no-wrap mode CR[3]=1) of 4-, 8-, 16-, or continuous-word burst mode, an output delay may occur when a burst sequence crosses its first device-row boundary (16word boundary). If the burst start address is 4-word boundary aligned, the delay does not occur. If the start address is misaligned to a 4-word boundary, the delay occurs once per burst-mode read sequence. The WAIT signal informs the system of this delay.
8.7
Burst Sequence (CR[7])
The burst sequence specifies the synchronous-burst mode data order (see Table 19, "Sequence and Burst Length" on page 53). When operating in a linear burst mode, either 4-, 8-, or 16-word burst length with the burst wrap bit (CR[3]) set, or in continuous burst mode, the device may incur an output delay when the burst sequence crosses the first 16-word boundary. (See Figure 17, "Word Boundary" on page 48 for word boundary description.) This depends on the starting address. If the starting address is aligned to a 4-word boundary, there is no delay. If the starting address is the end of a 4-word boundary, the output delay is one clock cycle less than the First Access Latency Count; this is the worst-case delay. The delay takes place only once, and only if the burst sequence crosses a 16-word boundary. The WAIT pin informs the system of this delay. For timing diagrams of WAIT functionality, see these figures:
* Figure 23, "Single Synchronous Read-Array Operation Waveform" on page 69 * Figure 24, "Synchronous 4-Word Burst Read Operation Waveform" on page 70 * Figure 25, "WAIT Functionality for EOWL (End-of-Word Line) Condition Waveform" on
page 71
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Datasheet
Intel(R) Wireless Flash Memory (W18)
Table 19. Sequence and Burst Length
Burst Addressing Sequence (Decimal) 4-Word Burst
CR[2:0]=0 01b
Start Addr. (Dec)
8-Word Burst
CR[2:0]=010b
16-Word Burst
CR[2:0]=011b
Continuous Burst
CR[2:0]=111b
Linear
Linear
Linear
Linear
0 1 2 3
Wrap (CR[3]=0)
0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
0-1-2...14-15 1-2-3...14-15-0 2-3-4...15-0-1 3-4-5...15-0-1-2 4-5-6...15-0-1-23 5-6-7...15-0-1...4 6-7-8...15-0-1...5 7-8-9...15-0-1...6
...
0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10... 5-6-7-8-9-10-11... 6-7-8-9-10-11-12... 7-8-9-10-11-1213...
...
4 5 6 7
...
14 15
...
...
14-15-0-1...13
14-15-16-17-18-1920-...
15-0-1-2-3...14
15-16-17-18-19-...
0 1 2 3
No-Wrap (CR[3]=1)
0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-910 4-5-6-7-8-9-1011 5-6-7-8-9-1011-12 6-7-8-9-10-1112-13 7-8-9-10-1112-13-14
0-1-2...14-15 1-2-3...15-16 2-3-4...16-17 3-4-5...17-18 4-5-6...18-19 5-6-7...19-20 6-7-8...20-21 7-8-9...21-22
...
0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10... 5-6-7-8-9-10-11... 6-7-8-9-10-11-12... 7-8-9-10-11-1213...
...
4 5 6 7
... ...
...
14 15
14-15...28-29 15-16...29-30
14-15-16-17-1819-20-... 15-16-17-18-1920-21-...
Datasheet
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Intel(R) Wireless Flash Memory (W18)
8.8
Clock Edge (CR[6])
Configuring the valid clock edge enables a flexible memory interface to a wide range of burst CPUs. Clock configuration sets the device to start a burst cycle, output data, and assert WAIT on the clock's rising or falling edge.
8.9
Burst Wrap (CR[3])
The burst wrap bit determines whether 4-, 8-, or 16-word burst accesses wrap within the burstlength boundary or whether they cross word-length boundaries to perform linear accesses. Nowrap mode (CR[3]=1) enables WAIT to hold off the system processor, as it does in the continuous burst mode, until valid data is available. In no-wrap mode (CR[3]=0), the device operates similarly to continuous linear burst mode but consumes less power during 4-, 8-, or 16-word bursts. For example, if CR[3]=0 (wrap mode) and CR[2:0] = 1h (4-word burst), possible linear burst sequences are 0-1-2-3, 1-2-3-0, 2-3-0-1, 3-0-1-2. If CR[3]=1 (no-wrap mode) and CR[2:0] = 1h (4-word burst length), then possible linear burst sequences are 0-1-2-3, 1-2-3-4, 2-3-4-5, and 3-4-5-6. CR[3]=1 not only enables limited nonaligned sequential bursts, but also reduces power by minimizing the number of internal read operations. Setting CR[2:0] bits for continuous linear burst mode (7h) also achieves the above 4-word burst sequences. However, significantly more power may be consumed. The 1-2-3-4 sequence, for example, consumes power during the initial access, again during the internal pipeline lookup as the processor reads word 2, and possibly again, depending on system timing, near the end of the sequence as the device pipelines the next 4-word sequence. CR[3]=1 while in 4-word burst mode (no-wrap mode) reduces this excess power consumption.
8.10
Burst Length (CR[2:0])
The Burst Length bit (BL[2:0]) selects the number of words the device outputs in synchronous read access of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word. Continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see Table 19, "Sequence and Burst Length" on page 53). When a burst cycle begins, the device outputs synchronous burst data until it reaches the end of the "burstable" address space.
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Intel(R) Wireless Flash Memory (W18)
9.0
Power Consumption
1.8 Volt Intel(R) Wireless Flash memory devices have a layered approach to power savings that can significantly reduce overall system power consumption. The APS feature reduces power consumption when the device is selected but idle. If CE# is deasserted, the memory enters its standby mode, where current consumption is even lower. Asserting RST# provides current savings similar to standby mode. The combination of these features can minimize memory power consumption, and therefore, overall system power consumption.
9.1
Active Power
With CE# at VIL and RST# at VIH, the device is in the active mode. Refer to Section 10.3, "DC Current Characteristics (.13 m and .18 m)" on page 58, for ICC values. When the device is in "active" state, it consumes the most power from the system. Minimizing device active current therefore reduces system power consumption, especially in battery-powered applications.
9.2
Automatic Power Savings (APS)
Automatic Power Saving (APS) provides low-power operation during a read's active state. During APS mode, ICCAPS is the average current measured over any 5 ms time interval 5 s after the following events happen:
* There is no internal sense activity; * CE# is asserted; * The address lines are quiescent, and at VSSQ or VCCQ.
OE# may be asserted during APS.
9.3
Standby Power
With CE# at VIH and the device in read mode, the flash memory is in standby mode, which disables most device circuitry and substantially reduces power consumption. Outputs are placed in a highimpedance state independent of the OE# signal state. If CE# transitions to VIH during erase or program operations, the device continues the operation and consumes corresponding active power until the operation is complete. ICCS is the average current measured over any 5 ms time interval 5 s after a CE# de-assertion.
9.4
Power-Up/Down Characteristics
The device is protected against accidental block erasure or programming during power transitions. Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together; so it doesn't matter whether VPP or VCC powers-up first. If VCCQ and/or VPP are not connected to the system supply, then VCC should attain VCCMIN before applying VCCQ and VPP. Device inputs should not be driven before supply voltage = VCCMIN. Power supply transitions should only occur when RST# is low.
Datasheet
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Intel(R) Wireless Flash Memory (W18)
9.4.1
System Reset and RST#
The use of RST# during system reset is important with automated program/erase devices because the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data. To allow proper CPU/flash initialization at system reset, connect RST# to the system CPU RESET# signal. System designers must guard against spurious writes when VCC voltages are above VLKO. Because both WE# and CE# must be low for a command write, driving either signal to VIH inhibits writes to the device. The CUI architecture provides additional protection because alteration of memory contents can only occur after successful completion of the two-step command sequences. The device is also disabled until RST# is brought to VIH, regardless of its control input states. By holding the device in reset (RST# connected to system PowerGood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection.
9.4.2
VCC, VPP, and RST# Transitions
The CUI latches commands issued by system software and is not altered by VPP or CE# transitions or WSM actions. Read-array mode is its power-up default state after exit from reset mode or after VCC transitions above VLKO (Lockout voltage). After completing program or block erase operations (even after VPP transitions below VPPLK), the Read Array command must reset the CUI to read-array mode if flash memory array access is desired.
9.5
Power Supply Decoupling
When the device is accessed, many internal conditions change. Circuits are enabled to charge pumps and switch voltages. This internal activity produces transient noise. To minimize the effect of this transient noise, device decoupling capacitors are required. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and proper decoupling capacitor selection suppresses these transient voltage peaks. Each flash device should have a 0.1 F ceramic capacitor connected between each power (VCC, VCCQ, VPP), and ground (VSS, VSSQ) signal. High-frequency, inherently low-inductance capacitors should be as close as possible to package signals.
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Intel(R) Wireless Flash Memory (W18)
10.0
10.1
Warning:
Thermal and DC Characteristics
Absolute Maximum Ratings
Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended, and extended exposure beyond the "Operating Conditions" may affect device reliability.
Notice: This datasheet contains information on products in the design phase of development. The information here is subject to change without notice. Do not finalize a design with this information.
Table 20. Absolute Maximum Ratings
Parameter Note Maximum Rating
Temperature under Bias Storage Temperature Voltage on Any Pin (except VCC, VCCQ, VPP) VPP Voltage VCC and VCCQ Voltage Output Short Circuit Current 1,2,3 1 4
-40 C to +85 C -65 C to +125 C -0.5 V to +2.45 V -0.2 V to +14 V -0.2 V to +2.45 V 100 mA
NOTES: 1. All specified voltages are relative to VSS. Minimum DC voltage is -0.5 V on input/output pins and -0.2 V on VCC and VPP pins. During transitions, this level may undershoot to -2.0 V for periods < 20 ns which, during transitions, may overshoot to VCC +2.0 V for periods < 20 ns. 2. Maximum DC voltage on VPP may overshoot to +14.0 V for periods < 20 ns. 3. VPP program voltage is normally VPP1. VPP can be 12 V 0.6 V for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. 4. Output shorted for no more than one second. No more than one output shorted at a time.
10.2
Operating Conditions
Table 21. Extended Temperature Operation (Sheet 1 of 2)
Symbol Parameter1 Note Min Nom Max Unit
TA VCC VCCQ VPP1 VPP2 tPPH
Operating Temperature VCC Supply Voltage I/O Supply Voltage I/O Supply Voltage (Extended) VPP Voltage Supply (Logic Level) Factory Programming VPP Maximum VPP Hours VPP = 12 V 3 3 4 2 2 2
-40 1.7 1.7 1.35 0.90 11.4
25 1.8 1.8 1.5 1.80 12.0
85 1.95 2.24 1.8 1.95 12.6 80
C
V
Hours
Datasheet
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Intel(R) Wireless Flash Memory (W18)
Table 21. Extended Temperature Operation (Sheet 2 of 2)
Symbol Parameter1 Note Min Nom Max Unit
Block Erase Cycles
Main and Parameter Blocks Main Blocks Parameter Blocks
VPP VCC VPP = 12 V VPP = 12 V
2 2 2
100,000 1000 2500 Cycles
NOTES: 1. See Section 10.3 and Section 10.4, "DC Voltage Characteristics" on page 60 for specific voltage-range specifications. 2. VPP is normally VPP1. VPP can be connected to 11.4 V-12.6 V for 1000 cycles on main blocks for extended temperatures and 2500 cycles on parameter blocks at extended temperature. 3. Contact your Intel field representative for VCC/VCCQ operations down to 1.65 V. 4. See the tables in Section 10.0, "Thermal and DC Characteristics" on page 57 and in Section 11.0, "AC Characteristics" on page 62 for operating characteristics within the Extended-VCCQ voltage range.
10.3
DC Current Characteristics (.13 m and .18 m)
Table 22. DC Current Characteristics (Sheet 1 of 3)
VCCQ=1.35 V - 1.8 V Sym Parameter (1) Note 32/64/128 Mbit Typ Max VCCQ= 1.8 V 32/64 Mbit Typ Max 128 Mbit Typ Max Unit Test Condition
ILI
Input Load
9
TBD
1
1
A
VCC = VCCMax VCCQ = VCCQMax VIN = VCCQ or GND VCC = VCCMax VCCQ = VCCQMax VIN = VCCQ or GND VCC = VCCMax VCCQ = VCCQMax CE# = VCC RST# =VSSQ VCC = VCCMax VCCQ = VCCQMax CE# = VSSQ RST# =VCCQ All other inputs =VCCQ or VSSQ
ILO .18 m ICCS .13 m ICCS .18 m ICCAPS
Output Leakage
DQ[15:0]
TBD
1
1
A
TBD VCC Standby 10 TBD TBD APS 11 TBD
TBD TBD TBD
5 8 5
18 50 18
5 8 5
25 A 70 25 A
.13 m ICCAPS
TBD
8
50
8
70
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Datasheet
Intel(R) Wireless Flash Memory (W18)
Table 22. DC Current Characteristics (Sheet 2 of 3)
VCCQ=1.35 V - 1.8 V Sym Parameter (1) Note 32/64/128 Mbit Typ Max VCCQ= 1.8 V 32/64 Mbit Typ Max 128 Mbit Typ Max Unit Test Condition
Asynchronous Page Mode f=13 MHz
2
TBD
TBD
3
6
4
7
mA
4 Word Read Burst length =4 Burst length =8 Burst length =16 Burst length = Continuous Burst length =4 Burst length =8 Burst length = 16 Burst length = Continuous Burst length =4 Burst length =8 Burst length = 16 Burst length = Continuous VCC = VCCMax CE# = VIL OE# = VIH Inputs = VIH or VIL VCC = VCCMax CE# = VIL OE# = VIH Inputs = VIH or VIL
TBD TBD 2 TBD TBD TBD TBD Synchronous CLK = 54 MHz 2 TBD TBD TBD Average VCC Read TBD 2, 3 TBD TBD TBD ICCW VCC Program 3,4,5 TBD TBD ICCE VCC Block Erase 3,4,5 TBD ICCWS ICCES VCC Program Suspend VCC Erase Suspend 6 6 TBD TBD
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
6 8 10 11 7 10 12 13 8 11 14 16 18 8 18 8 5 5
13 14 18 20 16 18 22 25 17 20 25 30 40 15 40 15 18 18
6 8 11 11 7 10 12 13 N.A. N.A. N.A. N.A. 18 8 18 8 5 5
13 14 19 20 16 18 22 25 N.A. N.A. N.A. N.A. 40 15 40 15 25 25
mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA A A
Synchronous CLK = 40 MHz ICCR Average VCC Read
ICCR
Synchronous CLK = 66 MHz
VPP = VPP1, Program in Progress VPP = VPP2, Program in Progress VPP = VPP1, Block Erase in Progress VPP = VPP2, Block Erase in Progress CE# = VCC, Program Suspended CE# = VCC, Erase Suspended
Datasheet
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Intel(R) Wireless Flash Memory (W18)
Table 22. DC Current Characteristics (Sheet 3 of 3)
VCCQ=1.35 V - 1.8 V Sym Parameter (1) Note 32/64/128 Mbit Typ Max VCCQ= 1.8 V 32/64 Mbit Typ Max 128 Mbit Typ Max Unit Test Condition
IPPS (IPPWS
,
IPPES) IPPR
VPP Standby VPP Program Suspend VPP Erase Suspend VPP Read
3
TBD
TBD
0.2
5
0.2
5
A
VPP TBD TBD
TBD TBD TBD TBD TBD
2 0.05 8 0.05 8
15 0.10 22 0.10 22
2 0.05 16 0.05 8
15 0.10
A
IPPW
VPP Program
4 TBD TBD 37 0.10
mA
VPP = VPP2, Program in Progress VPP = VPP1, Erase in Progress VPP = VPP2, Erase in Progress
IPPE
VPP Erase
4 TBD 22
mA
NOTES: 1. All currents are RMS unless noted. Typical values at typical VCC, TA = +25C. 2. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation. See ICCRQ specification for details. 3. Sampled, not 100% tested. 4. VCC read + program current is the sum of VCC read and VCC program currents. 5. VCC read + erase current is the sum of VCC read and VCC erase currents. 6. ICCES is specified with device deselected. If device is read while in erase suspend, current is ICCES plus ICCR. 7. VPP <= VPPLK inhibits erase and program operations. Don't use VPPL and VPPH outside their valid ranges. 8. VIL can undershoot to -0.4V and VIH can overshoot to VCCQ+0.4V for durations of 20 ns or less. 9. If VIN>VCC the input load current increases to 10 A max. 10.ICCS is the average current measured over any 5ms time interval 5s after a CE# de-assertion. 11.Refer to section Section 9.2, "Automatic Power Savings (APS)" on page 55 for ICCAPS measurement details. 12.TBD values are to be determined pending silicon characterization.
10.4
DC Voltage Characteristics
Table 23. DC Voltage Characteristics (Sheet 1 of 2)
VCCQ=1.35 V - 1.8 V Sym Parameter (1) Note 32/64/128 Mbit Min Max VCCQ= 1.8 V 32/64 Mbit Min Max 128 Mbit Min Max Unit Test Condition
VIL VIH VOL
Input Low Input High Output Low
8
0 VCCQ - 0.2
0.2 VCCQ 0.1
0 VCCQ - 0.4
0.4 VCCQ 0.1
0 VCCQ - 0.4
0.4 VCCQ 0.1
V V VCC = VCCMin VCCQ = VCCQMin IOL = 100 A
V
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Datasheet
Intel(R) Wireless Flash Memory (W18)
Table 23. DC Voltage Characteristics (Sheet 2 of 2)
VCCQ=1.35 V - 1.8 V Sym Parameter (1) Note 32/64/128 Mbit Min Max VCCQ= 1.8 V 32/64 Mbit Min Max 128 Mbit Min Max Unit Test Condition
VOH
Output High
VCCQ - 0.1 7 0.4 1.0 TBD
VCCQ - 0.1 0.4 1.0 0.9
VCCQ - 0.1 0.4 1.0 0.9
V V V V
VCC = VCCMin VCCQ = VCCQMin IOH = -100 A
VPPLK VLKO VILKOQ
VPP Lock-Out VCC Lock VCCQ Lock
NOTE: For all numbered note references in this table, refer to the notes in Table 22, "DC Current Characteristics" on page 58.
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61
Intel(R) Wireless Flash Memory (W18)
11.0
11.1
AC Characteristics
Read Operations - .13 m Lithography
VCCQ= 1.35 V - 1.8 V VCCQ= 1.7 V - 2.24 V -60 Min Max Min -80 Max Unit
Table 24. Read Operations-- .13 m Lithography (Sheet 1 of 2)
#
Sym
Parameter 1,2
Notes Min
-65 Max Min
-85 Max
Asynchronous Specifications
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10
tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tOH
Read Cycle Time Address to Output Valid CE# Low to Output Valid OE# Low to Output Valid RST# High to Output Valid CE# Low to Output Low-Z OE# Low to Output Low-Z CE# High to Output High-Z OE# High to Output High-Z CE# (OE#) High to Output Low-Z
7,8 7,8 7,8 4
65 65 65 25 150
85 85 85 30 150 0 0 17 14 20 14 0
60 60 60 20 150 0 0 14 14 0
80 80 80 25 150 0 0 17 14 0
ns ns ns ns ns ns ns ns ns ns
5 4,5 5 4,5 4,5
0 0
0
Latching Specifications
R101 R102 R103 R104 R105 R106 R108
tAVVH tELVH tVLQV tVLVH tVHVL tVHAX tAPA
Address Setup to ADV# High CE# Low to ADV# High ADV# Low to Output Valid ADV# Pulse Width Low ADV# Pulse Width High Address Hold from ADV# High Page Address Access Time 3 7,8
7 10 65 7 7 7 25
7 10 85 7 7 7 30
7 10 60 7 7 7 20
7 10 80 7 7 7 25
ns ns ns ns ns ns ns
Clock Specifications
R200 R201 R202 R203
fCLK tCLK tCH/L tCHCL
CLK Frequency CLK Period CLK High or Low Time CLK Fall or Rise Time 18.5 4.5
54 25 9.5 3
40 15 3.5 3
66 18.5 4.5 3
54
MHz ns ns
3
ns
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Intel(R) Wireless Flash Memory (W18)
Table 24. Read Operations-- .13 m Lithography (Sheet 2 of 2)
VCCQ= 1.35 V - 1.8 V # Sym Parameter 1,2 Notes Min Synchronous Specifications -65 Max Min -85 Max Min VCCQ= 1.7 V - 2.24 V -60 Max Min -80 Max Unit
R301 R302 R303 R304 R305 R306 R307 R308 R309 R310
tAVCH tVLCH tELCH tCHQV tCHQX tCHAX tCHTV tELTV tEHTZ tEHEL
Address Valid Setup to CLK ADV# Low Setup to CLK CE# Low Setup to CLK CLK to Output Valid Output Hold from CLK Address Hold from CLK CLK to WAIT Valid CE# Low to WAIT Valid CE# High to WAIT High-Z CE# Pulse Width High 3 8 6 5,6 6 8
7 7 7 14 3 7 14 14 14 14
7 7 7 20 3 7 20 20 20 14
7 7 7 11 3 7 11 11 11 14
7 7 7 14 3 7 14 14 14 14
ns ns ns ns ns ns ns ns ns ns
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63
Intel(R) Wireless Flash Memory (W18)
11.2
Read Operations - .18 m Lithography
32/64 Mbit 128 Mbit -85 Min Max Min -85 Max Unit
Table 25. Read Operations -- .18 m Lithography (Sheet 1 of 2)
#
Sym
Parameter (1,2)
Notes Min
-70 Max
Asynchronous Specifications
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10
tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tOH
Read Cycle Time Address to Output Delay CE# Low to Output Delay OE# Low to Output Delay RST# High to Output Delay CE# Low to Output in Low-Z OE# Low to Output in Low-Z CE# High to Output in High-Z OE# High to Output in High-Z CE# (OE#) High to Output in Low-Z 5 4,5 5 4,5 4,5 4
70 70 70 30 150 0 0 20 14 0
85 85 85 30 150 0 0 20 14 0
85 85 85 30 150 0 0 20 14 0
ns ns ns ns ns ns ns ns ns ns
Latching Specifications
R101 R102 R103 R104 R105 R106 R108
tAVVH tELVH tVLQV tVLVH tVHVL tVHAX tAPA
Address Setup to ADV# High CE# Low to ADV# High ADV# Low to Output Delay ADV# Pulse Width Low ADV# Pulse Width High Address Hold from ADV# High Page Address Access Time 3
10 10 70 10 10 9 20
10 10 85 10 10 9 25
10 10 85 10 10 9 25
ns ns ns ns ns ns ns
Clock Specifications
R200 R201 R202 R203
fCLK tCLK tCH/L tCHCL
CLK Frequency CLK Period CLK High or Low Time CLK Fall or Rise Time 19 5
52 25 5 3
40 25 5 3
40
MHz ns ns
3
ns
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Datasheet
Intel(R) Wireless Flash Memory (W18)
Table 25. Read Operations -- .18 m Lithography (Sheet 2 of 2)
32/64 Mbit # Sym Parameter (1,2) Notes Min Synchronous Specifications -70 Max Min -85 Max Min 128 Mbit -85 Max Unit
R301 tAVCH R302 tVLCH R303 tELCH R304 tCHQV R305 tCHQX R306 tCHAX R307 tCHTV R308 tELTV R309 tEHTZ R310 tEHEL
Address Valid Setup to CLK ADV# Low Setup to CLK CE# Low Setup to CLK CLK to Output Valid Output Hold from CLK Address Hold from CLK CLK to WAIT Valid CE# Low to WAIT Valid CE# High to WAIT High-Z CE# Pulse Width High 6 5,6 6 3
9 10 9 14 3.5 10 14 14 20 15
9 10 9 18 3.5 10 18 18 25 20
9 10 9 18 3.5 10 18 18 25 20
ns ns ns ns ns ns ns ns ns ns
NOTES: 1. See Figure 34, "AC Input/Output Reference Waveform" on page 81 for timing measurements and maximum allowable input slew rate. 2. AC specifications assume the data bus voltage is less than or equal to VCCQ when a read operation is initiated. 3. Address hold in synchronous-burst mode is defined as tCHAX or tVHAX, whichever timing specification is satisfied first. 4. OE# may be delayed by up to tELQV- tGLQV after the falling edge of CE# without impact to tELQV. 5. Sampled, not 100% tested. 6. Applies only to subsequent synchronous reads. 7. During the initial access of a synchronous burst read, data from the first word may begin to be driven onto the data bus as early as the first clock edge after tAVQV. 8. All specs above apply to all densities.
x
Datasheet
65
Intel(R) Wireless Flash Memory (W18)
Figure 20. Asynchronous Read Operation Waveform
R1
Address [A]
VIH VIL R2
Valid Address
CE# [E]
VIH VIL R3 R8 R4
OE# [G]
VIH VIL R7
R9
WE# [W]
VIH VIL VOH VOL
High Z High Z
WAIT [T]
Note 1
Data [D/Q]
VOH VOL
High Z
Valid Output
R5
R10
RST# [P]
VIH VIL
NOTES:. 1. WAIT shown asserted (CR.10=0) 2. ADV# assumed to be driven to VIL in this waveform
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Intel(R) Wireless Flash Memory (W18)
Figure 21. Latched Asynchronous Read Operation Waveform
R1
A[MAX:2] [A]
VIH VIL
Valid Address
Valid Address
A[1:0] [A]
VIH VIL R2 R101 R105 R106
Valid Address
Valid Address
ADV# [V]
VIH VIL R104 R103
CE# [E]
VIH VIL R102
R3
R4 R6
R8
OE# [G]
VIH VIL R7 R9
WE# [W]
VIH VIL
Data [Q]
VOH VOL
High Z
Valid Output
R5
R10
RST# [P]
VIH VIL
Datasheet
67
Intel(R) Wireless Flash Memory (W18)
Figure 22. Page-Mode Read Operation Waveform
R1
A[MAX:2] [A]
VIH VIL
Valid Address
R2
A[1:0] [A]
VIH VIL R101 R105 R106
Valid Address
Valid Address
Valid Address
Valid Address
ADV# [V]
VIH VIL R104 R103
CE# [E]
VIH VIL R102
R3
R4 R6
R8
OE# [G]
VIH VIL R7 R9
WE# [W] WAIT [T]
VIH VIL VOH VOL VOH VOL R5
High Z Valid Output Valid Output Valid Output Valid Output High Z
Note 1
R108
High Z
Data [D/Q]
R10
RST# [P]
VIH VIL
NOTE: WAIT shown asserted (CR.10 = 0).
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Datasheet
Intel(R) Wireless Flash Memory (W18)
Figure 23. Single Synchronous Read-Array Operation Waveform
CLK [C]
VIH VIL R301 R306 Note 1
Address [A]
VIH VIL
Valid Address
R2 R101 R105 R106 R302
ADV# [V]
VIH VIL
R104 R103
CE# [E]
VIH VIL R102
R3
R4
R8
OE# [G]
VIH VIL R303 R7 R9
WE# [W]
VIH VIL R308 R309 R10 Note 2 R304 R305
Valid Output High Z
WAIT [T]
VOH VOL
High Z
Data [Q]
VOH VOL
High Z
R5
RST# [P]
VIH VIL
NOTES: 1. Section 8.2, "First Access Latency Count (CR[13:11])" on page 48 describes how to insert clock cycles during the initial access. 2. WAIT (shown asserted; CR.10=0) can be configured to assert either during, or one data cycle before, valid data. 3. This waveform illustrates the case in which an x-word burst is initiated to the main array and it is terminated by a CE# de-assertion after the first word in the burst. If this access had been done to Status, ID, or Query reads, the asserted (low) WAIT signal would have remained asserted (low) as long as CE# is asserted (low).
Datasheet
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Intel(R) Wireless Flash Memory (W18)
Figure 24. Synchronous 4-Word Burst Read Operation Waveform
CLK [C]
VIH VIL 0 R301 1 R306 Note 1
Address [A]
VIH VIL
Valid Address
R2 R101 R105 R106 R302
ADV# [V]
VIH VIL
R104 R103 R310 R3
CE# [E]
VIH VIL R102
R4
R8
OE# [G]
VIH VIL R303 R7 R9
WE# [W]
VIH VIL R308 R307 R309 R10
High Z
WAIT [T]
VOH VOL
High Z
Note 2 R304 R305
Valid Output Valid Output Valid Output Valid Output
Data [Q]
VOH VOL
High Z
High Z
R5
RST# [P]
VIH VIL
NOTES: 1. Section 8.2, "First Access Latency Count (CR[13:11])" on page 48 describes how to insert clock cycles during the initial access. 2. WAIT (shown asserted; CR.10 = 0) can be configured to assert either during, or one data cycle before, valid data.
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Intel(R) Wireless Flash Memory (W18)
Figure 25. WAIT Functionality for EOWL (End-of-Word Line) Condition Waveform
VIH VIL 0 R301 1 R306
CLK [C]
Note 1
Address [A]
VIH VIL
Valid Address
R2 R101 R105 R106 R302
ADV# [V]
VIH VIL
R104 R103
CE# [E]
VIH VIL R102
R3
R4
OE# [G]
VIH VIL R303 R7
WE# [W]
VIH VIL R308 R307
WAIT [T]
VOH VOL
High Z
Note 2 R304 R305
Valid Output Valid Output Valid Output Valid Output
High Z
Data [D/Q]
VOH VOL
High Z
R5
RST# [P]
VIH VIL
NOTES: 1. Section 8.2, "First Access Latency Count (CR[13:11])" on page 48 describes how to insert clock cycles during the initial access. 2. WAIT (shown asserted; CR.10=0) can be configured to assert either during, or one data cycle before, valid data. (assumed wait delay of two clocks for example)
Datasheet
71
Intel(R) Wireless Flash Memory (W18)
Figure 26. WAIT Signal in Synchronous Non-Read Array Operation Waveform
CLK [C]
VIH Note 1 VIL R301 R306
Address [A]
VIH VIL
Valid Address
R2 R101 R105 R106 R302
ADV# [V]
VIH VIL
R104 R103
CE# [E]
VIH VIL R102
R3
R4
R8
OE# [G]
VIH VIL R303 R7 R9
WE# [W]
VIH VIL R308 R309 R10 Note 2 R304 R305
Valid Output High Z
WAIT [T]
VOH VOL
High Z
Data [Q]
VOH VOL
High Z
R5
RST# [P]
VIH VIL
NOTES: 1. Section 8.2, "First Access Latency Count (CR[13:11])" on page 48 describes how to insert clock cycles during the initial access. 2. WAIT shown asserted (CR.10=0).
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Intel(R) Wireless Flash Memory (W18)
Figure 27. Burst Suspend
R304 CLK R1 R2 Address [A] R101 R105 ADV# R3 CE# [E] R4 OE# [G] R13 R12 WAIT [T] WE# [W] R7 R6 DATA [D/Q] Q0 R304 Q1 Q1 R304 Q2 R9 R4 R9 R8 R305 R305 R305
R106
NOTE: 1. During Burst Suspend Clock signal can be held high or low
Datasheet
73
Intel(R) Wireless Flash Memory (W18)
11.3
AC Write Characteristics .13 m Lithography
VCCQ= 1.35 V - 1.8 V VCCQ= 1.7 V - 2.24 V -60 Min Max -80 Min Max Unit Notes
Table 26. AC Write Characteristics -
#
Sym
Parameter 1,2
-65 Min Max
-85 Min Max
W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12
tPHWL (tPHEL) tELWL (tWLEL) tWLWH (tELEH) tDVWH (tDVEH) tAVWH (tAVEH) tWHEH (tEHWH)
RST# High Recovery to WE# (CE#) Low CE# (WE#) Setup to WE# (CE#) Low WE# (CE#) Write Pulse Width Low Data Setup to WE# (CE#) High Address Setup to WE# (CE#) High CE# (WE#) Hold from WE# (CE#) High
3
150 0
150 0 60 60 60 0 0 0 25 200 0 0 200 0 tAVQV + 55 0 20 20
150 0 40 40 40 0 0 0 20 200 0 0 200 0 tAVQV +20 0 12 12
150 0 60 60 60 0 0 0 25 200 0 0 200 0 tAVQV +50 0 20 20
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4
50 50 50 0 0 0
tWHDX (tEHDX) Data Hold from WE# (CE#) High tWHAX (tEHAX) tWHWL (tEHEL) tVPWH (tVPEH) tQVVL tQVBL Address Hold from WE# (CE#) High WE# (CE#) Pulse Width High VPP Setup to WE# (CE#) High VPP Hold from Valid SRD WP# Hold from Valid SRD 5,6,7 3 3,8 3,8 3
20 200 0 0 200 0
W13 tBHWH (tBHEH) WP# Setup to WE# (CE#) High W14 W16 W18 W19 W20 tWHGL (tEHGL) tWHQV tWHAV tWHCV tWHVH Write Recovery before Read WE# High to Valid Data WE# High to Address Valid WE# High to CLK Valid WE# High to ADV# High
3,6,10 3,9,10 3,10 3,10
tAVQV + 25 0 16 16
NOTES: 1. Write timing characteristics during erase suspend are the same as during write-only operations. 2. A write operation can be terminated with either CE# or WE#. 3. Sampled, not 100% tested. 4. Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high (whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH. 5. Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever is first) to CE# or WE# low (whichever is last). Hence, tWHWL = tEHEL = tWHEL = tEHWL. 6. System designers should take this into account and may insert a software No-Op instruction to delay the first read after issuing a command. 7. For commands other than resume commands. 8. VPP should be held at VPP1 or VPP2 until block erase or program success is determined. 9. Applicable during asynchronous reads following a write. 10.tWHCH/L OR tWHVH must be met when transitioning from a write cycle to a synchronous burst read. tWHCH/L and tWHVH both refer to the address latching event (either the rising/falling clock edge or the rising ADV# edge, whichever occurs first).
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Intel(R) Wireless Flash Memory (W18)
l
Table 27. AC Write Characteristics -
.18 m Lithography
32-Mbit 64-Mbit 128-Mbit
#
Sym
Parameter 1,2
Notes -70 Min Max Min -85 Max
Unit
W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W16 W18 W19 W20
tPHWL (tPHEL) tELWL (tWLEL) tWLWH (tELEH) tDVWH (tDVEH) tAVWH (tAVEH) tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tWHWL (tEHEL) tVPWH (tVPEH) tQVVL tQVBL tBHWH (tBHEH) tWHGL (tEHGL) tWHQV tWHAV tWHCV tWHVH
RST# High Recovery to WE# (CE#) Low CE# (WE#) Setup to WE# (CE#) Low WE# (CE#) Write Pulse Width Low Data Setup to WE# (CE#) High Address Setup to WE# (CE#) High CE# (WE#) Hold from WE# (CE#) High Data Hold from WE# (CE#) High Address Hold from WE# (CE#) High WE# (CE#) Pulse Width High VPP Setup to WE# (CE#) High VPP Hold from Valid SRD WP# Hold from Valid SRD WP# Setup to WE# (CE#) High Write Recovery before Read WE# High to Valid Data WE# High to Address Valid WE# High to CLK Valid WE# High to ADV# High
3
150 0
150 0 60 60 60 0 0 0 25 200 0 0 200 0 tAVQV + 50 0 20 20
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4
45 45 45 0 0 0
5,6,7 3 3,8 3,8 3
25 200 0 0 200 0
3,6,10 3,9,10 3,10 3,10
tAVQV + 40 0 20 20
NOTES: 1. Write timing characteristics during erase suspend are the same as during write-only operations. 2. A write operation can be terminated with either CE# or WE#. 3. Sampled, not 100% tested. 4. Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high (whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH. 5. Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever is first) to CE# or WE# low (whichever is last). Hence, tWHWL = tEHEL = tWHEL = tEHWL. 6. System designers should take this into account and may insert a software No-Op instruction to delay the first read after issuing a command. 7. For commands other than resume commands. 8. VPP should be held at VPP1 or VPP2 until block erase or program success is determined. 9. Applicable during asynchronous reads following a write. 10.tWHCH/L OR tWHVH must be met when transitioning from a write cycle to a synchronous burst read. tWHCH/L and tWHVH both refer to the address latching event (either the rising/falling clock edge or the rising ADV# edge, whichever occurs first).
Datasheet
75
Intel(R) Wireless Flash Memory (W18)
Figure 28. Write Operations Waveform
CLK [C]
VIH VIL W19
Note 1
Note 2
Valid Address
Note 3
Valid Address
Note 4
Note 5
Valid Address
Address [A]
VIH VIL
W5 W18 R101 R105 R106 W8
ADV# [V]
VIH VIL R104 W20
CE# (WE#) [E(W)]
VIH VIL W2 W6
Note 6
OE# [G]
VIH VIL W3 W9 W14
WE# (CE#) [W(E)]
VIH VIL W1 W7 W16
Note 6
Data [Q]
VIH
Data In Data In
VIL W4
Valid SRD
RST# [P]
VIH VIL W13 W12
WP# [B]
VIH VIL W10
VPPH
W11
VPP [V]
VPPLK VIL
NOTES: 1. VCC power-up and standby. 2. Write Program or Erase Setup command. 3. Write valid address and data (for program) or Erase Confirm command. 4. Automated program/erase delay. 5. Read status register data (SRD) to determine program/erase operation completion. 6. OE# and CE# must be asserted and WE# must be deasserted for read operations. 7. CLK is ignored. (but may be kept active/toggling)
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Intel(R) Wireless Flash Memory (W18)
Figure 29. Asynchronous Read to Write Operation Waveform
R1 R2 Address [A] R3 CE# [E} R4 OE# [G] W3 W2 WE# [W] R7 R6 Data [D/Q] R5 RST# [P] Q W7 R10 W4 D W6 R9 R8 W5 W8
Figure 30. Asynchronous Write to Read Operation
W5 Address [A] W2 CE# [E} W3 WE# [W]
W8
R1
W6
R10
W18
W14 OE# [G] R4 R2 R3 Q
W7 W4 Data [D/Q] W1 RST # [P] D
R9 R8
Datasheet
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Intel(R) Wireless Flash Memory (W18)
Figure 31. Synchronous Read to Write Operation
Latency Count R301 R302 R306 CLK [C] R2 R101 Address [A] R105 R106 R102 ADV# [V] R303 R3 CE# [E] R4 R8 OE# [G] W15 W3 W2 WE# R12 WAIT [T] R304 R7 Data [D/Q] Q R305 D R13 W7 D R307 W19 W9 W8 R11 W6 R104 W20 W5 W18
Figure 32. Synchronous Write To Read Operation
Lat ency Count R302 R301 R2 CLK W5 Address [A] W20 ADV# W6 W2 CE# [E} W18 W19 R11 R303 R106 R104 W8 R306
W3 WE# [W]
R4 OE# [G ] R12 WAIT [T] W7 W4 Data [D/Q ] W1 RST# [P] D R3 Q R304 R304 R305 Q R307
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Intel(R) Wireless Flash Memory (W18)
11.4
Erase and Program Times
Table 28. Erase and Program Times
Operation Symbol Parameter Description1 VPP1 Notes Typ Erasing and Suspending Max Typ Max VPP2 Unit
W500 Erase Time Suspend Latency
Programming
tERS/PB tERS/MB tSUSP/P tSUSP/E
4-Kword Parameter Block 32-Kword Main Block Program Suspend Erase Suspend
2,3 2,3 2 2
0.3 0.7 5 5
2.5 4 10 20
0.25 0.4 5 5
2.5 4 10 20
s s s s
W501 W600 W601
W200 Program Time W201 W202
tPROG/W tPROG/PB tPROG/MB
5
Single Word 4-Kword Parameter Block 32-Kword Main Block
2 2,3 2,3
12 0.05 0.4
150 .23 1.8
8 0.03 0.24
130 0.07 0.6
s s s
Enhanced Factory Programming
W400 Program W401 W402 W403 Operation Latency W404 W405
tEFP/W tEFP/PB tEFP/MB tEFP/SETUP tEFP/TRAN tEFP/VERIFY
Single Word 4-Kword Parameter Block 32-Kword Main Block EFP Setup Program to Verify Transition Verify
4 2,3 2,3
N/A N/A N/A
N/A
3.1 15 120
16
s ms ms
N/A N/A N/A N/A N/A 2.7 1.7
5 5.6 130
s s s
NOTES: 1. Unless noted otherwise, all parameters are measured at TA = +25 C and nominal voltages, and they are sampled, not 100% tested. 2. Excludes external system-level overhead. 3. Exact results may vary based on system overhead. 4. W400-Typ is the calculated delay for a single programming pulse. W400-Max includes the delay when programming within a new word-line. 5. Some EFP performance degradation may occur if block cycling exceeds 10.
Datasheet
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Intel(R) Wireless Flash Memory (W18)
11.5
Reset Specifications
Table 29. Reset Specifications
# Symbol Parameter1 Notes Min Max Unit
P1 P2 P3
tPLPH tPLRH tVCCPH
RST# Low to Reset during Read RST# Low to Reset during Block Erase RST# Low to Reset during Program VCC Power Valid to Reset
1, 2, 3, 4 1, 3, 4, 5 1, 3, 4, 5 1,3,4,5,6
100 20 10 60
ns s s s
NOTES: 1. These specifications are valid for all product versions (packages and speeds). 2. The device may reset if tPLPH< tPLPHMin, but this is not guaranteed. 3. Not applicable if RST# is tied to VCC. 4. Sampled, but not 100% tested. 5. If RST# is tied to VCC, the device is not ready until tVCCPH occurs after when VCC VCCMin. 6. If RST# is tied to any supply/signal with VCCQ voltage levels, the RST# input voltage must not exceed VCC until VCC VCCMin.
Figure 33. Reset Operations Waveforms
P1
R5
(A) Reset during read mode
RST# [P]
VIH VIL
P2
(B) Reset during program or block erase P1 P2
Abort Complete
R5
RST# [P]
VIH VIL
P2
(C) Reset during program or block erase P1 P2
Abort Complete
R5
RST# [P]
VIH VIL
P3
(D) VCC Power-up to RST# high
VCC
VCC 0V
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11.6
AC I/O Test Conditions
Figure 34. AC Input/Output Reference Waveform
VCCQ Input 0V
NOTE: Input timing begins, and output timing ends, at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed conditions are when VCC = VCCMin.
VCCQ /2
Test Points
VCCQ/2
Output
Figure 35. Transient Equivalent Testing Load Circuit
VCCQ R1
Device Under Test
Out CL R2
NOTE: See Table 17 for component values.
Table 30. Test Configuration Component Values for Worst Case Speed Conditions
Test Configuration CL (pF) R1 (k) R2 (k)
VCCQMin-Extended (1.35 V) Standard Test VCCQMin (1.7 V) Standard Test
NOTE: CL includes jig capacitance.
30 30
13.5 16.7
13.5 16.7
Figure 36. Clock Input AC Waveform
R201
CLK [C]
VIH VIL R202 R203
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Intel(R) Wireless Flash Memory (W18)
11.7
Device Capacitance
TA = +25 C, f = 1 MHz
Symbol Parameter Typ Max Unit Condition
CIN COUT CCE
Input Capacitance Output Capacitance CE# Input Capacitance
6 8 10
8 12 12
pF pF pF
VIN = 0.0 V VOUT = 0.0 V VIN = 0.0 V
Sampled, not 100% tested.
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Appendix A Write State Machine States
This table shows the command state transitions based on incoming commands. Only one partition can be actively programming or erasing at a time. Figure 37. Write State Machine -- Next State Table (Sheet 1 of 2)
Chip Next State after Command Input Current Chip
Read Array
(3)
Program Setup
(4,5)
Erase Setup
(4,5)
Write State Machine (WSM) Next State Table
State
Ready Lock/CR Setup OTP
(8)
Enhanced BE Confirm, Factory P/E Resume, Pgm ULB Setup
(4)
Confirm (D0H)
(9)
Program/ Erase Suspend (B0H)
Read Status
Clear Status Register (50H)
(6)
Read ID/Query
(FFH) Ready
(10H/40H) Program Setup
(20H) Erase Setup
(30H) EFP Setup
(70H) Ready
(90H, 98H)
Ready (Lock Error) Setup Busy Setup
Ready OTP Busy Program Busy
Ready (Lock Error)
Program
Busy Suspend Setup Busy
Program Busy Program Suspend Ready (Error) Erase Busy Erase Suspend Pgm in Erase Susp Setup Erase Suspend Erase Busy Pgm Busy Erase Busy
Pgm Susp
Program Busy Program Suspend Ready (Error)
Erase Susp
Erase Busy Erase Suspend
Erase Suspend Setup Program in Erase Suspend Busy Suspend Lock/CR Setup in Erase Suspend Enhanced Factory Program Setup EFP Busy EFP Verify
Program in Erase Suspend Busy Program in Erase Suspend Busy Program Suspend in Erase Suspend Erase Suspend (Lock Error) Ready (Error) Pgm in Erase Susp Busy Erase Susp EFP Busy EFP Busy
(7) (7)
Pgm Susp in Erase Susp
Program in Erase Suspend Busy
Program Suspend in Erase Suspend Erase Suspend (Lock Error) Ready (Error)
Verify Busy
Output Next State after Command Input
Output Next State Table
Pgm Setup, Erase Setup, OTP Setup, Pgm in Erase Susp Setup, EFP Setup, EFP Busy, Verify Busy Lock/CR Setup, Lock/CR Setup in Erase Susp OTP Busy Ready, Pgm Busy, Pgm Suspend, Erase Busy, Erase Suspend, Pgm In Erase Susp Busy, Pgm Susp In Erase Susp
(1)
Status
Status Status
Array
(3)
Status
Output does not change
Status
Output does not change
ID/Query
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Intel(R) Wireless Flash Memory (W18)
Figure 37. Write State Machine -- Next State Table (Sheet 2 of 2)
Chip Next State after Command Input Current Chip
Lock, Unlock, Lock-down, CR setup (60H) Ready Lock/CR Setup OTP Setup Busy Setup Program Busy Suspend Setup Busy Erase Suspend Setup Program in Erase Suspend Busy Suspend Lock/CR Setup in Erase Suspend Enhanced Factory Program Setup EFP Busy EFP Verify EFP Busy
(7) (7) (5)
OTP Setup
(5)
Lock Block Confirm (01H)
(9)
Write State Machine (WSM) Next State Table
State
(8)
LockDown Block Confirm (2FH)
(9)
Write CR Confirm
(9)
Enhanced Fact Pgm Exit (blk add <> WA0) (XXXXH)
Illegal commands or EFP data
(2)
WSM Operation Completes
(C0H) OTP Setup
(03H) Ready
(other codes)
Lock/CR Setup
Ready (Lock Error)
Ready
Ready OTP Busy
Ready
Ready (Lock Error)
N/A
Ready Program Busy Program Busy Program Suspend Ready (Error) Erase Busy Lock/CR Setup in Erase Susp Erase Suspend Program in Erase Suspend Busy Program in Erase Suspend Busy Program Suspend in Erase Suspend Erase Suspend (Lock Error) Erase Susp Erase Susp Erase Susp Ready (Error) EFP Verify Ready EFP Busy
(7) (7)
N/A Ready N/A Erase Busy Ready
N/A
Erase Suspend
Erase Suspend (Lock Error)
N/A
Verify Busy
EFP Verify
Ready
Output Next State after Command Input
Output Next State Table
Pgm Setup, Erase Setup, OTP Setup, Pgm in Erase Susp Setup, EFP Setup, EFP Busy, Verify Busy Lock/CR Setup, Lock/CR Setup in Erase Susp OTP Busy Ready, Pgm Busy, Pgm Suspend, Erase Busy, Erase Suspend, Pgm In Erase Susp Busy, Pgm Susp In Erase Susp Status
(1)
Status
Array
Status
Output does not change
Status
Output does not change
Array
Output does not change
NOTES: 1. The output state shows the type of data that appears at the outputs if the partition address is the same as the command address. A partition can be placed in Read Array, Read Status or Read ID/CFI, depending on the command issued. Each partition stays in its last output state (Array, ID/CFI or Status) until a new command changes it. The next WSM state does not depend on the partition's output state. For example, if partition #1's output state is Read Array and partition #4's output state is Read Status, every read from partition #4 (without issuing a new command) outputs the Status register.
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2. Illegal commands are those not defined in the command set. 3. All partitions default to Read Array mode at power-up. A Read Array command issued to a busy partition results in undermined data when a partition address is read. 4. Both cycles of 2 cycles commands should be issued to the same partition address. If they are issued to different partitions, the second write determines the active partition. Both partitions will output status information when read. 5. If the WSM is active, both cycles of a 2 cycle command are ignored. This differs from previous Intel devices. 6. The Clear Status command clears status register error bits except when the WSM is running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, EFP modes) or suspended (Erase Suspend, Pgm Suspend, Pgm Suspend In Erase Suspend). 7. EFP writes are allowed only when status register bit SR.0 = 0. EFP is busy if Block Address = address at EFP Confirm command. Any other commands are treated as data. 8. The "current state" is that of the WSM, not the partition. 9. Confirm commands (Lock Block, Unlock Block, Lock-down Block, Configuration Register) perform the operation and then move to the Ready State. 10.In Erase suspend, the only valid two cycle commands are "Program Word", "Lock/Unlock/Lockdown Block", and "CR Write". Both cycles of other two cycle commands ("OEM CAM program & confirm", "Program OTP & confirm", "EFP Setup & confirm", "Erase setup & confirm") will be ignored. In Program suspend or Program suspend in Erase suspend, both cycles of all two cycle commands will be ignored.
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Appendix B Common Flash Interface
This appendix defines the data structure or "database" returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. The Query is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface, or CFI.
B.1
Query Structure Output
The Query database allows system software to obtain information for controlling the flash device. This section describes the device's CFI-compliant interface that allows access to Query data. Query data are presented on the lowest-order data outputs (DQ0-7) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this family of devices, the Query table device starting address is a 10h, which is a word address for x16 devices. For a word-wide (x16) device, the first two Query-structure bytes, ASCII "Q" and "R," appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00h data on upper bytes. The device outputs ASCII "Q" in the low byte (DQ0-7) and 00h in the high byte (DQ8-15). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. In all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been dropped. In addition, since the upper byte of word-wide devices is always "00h," the leading "00" has been dropped from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.
Table 31. Summary of Query Structure Output as a Function of Device and Mode
Device Device Addresses Hex Offset 00010: 00011: 00012: Hex Code 51 52 59 ASCII Value "Q" "R" "Y"
Table 32. Example of Query Structure Output of x16- and x8 Devices
Offset AX-A0 00010h 00011h 00012h 00013h 00014h 00015h 00016h 00017h 00018h ... Word Addressing: Hex Code D15-D0 0051 0052 0059 P_IDLO P_IDHI PLO PHI A_IDLO A_IDHI ... Value "Q" "R" "Y" PrVendor ID # PrVendor TblAdr AltVendor ID # ... Offset AX-A0 00010h 00011h 00012h 00013h 00014h 00015h 00016h 00017h 00018h ... Byte Addressing: Hex Code Value D7-D0 51 "Q" 52 "R" 59 "Y" P_IDLO PrVendor P_IDLO ID # P_IDHI ID # ... ...
Intel(R) Wireless Flash Memory (W18)
B.2
Query Structure Overview
The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or "database." The structure sub-sections and address locations are summarized below.
Table 33. Query Structure
Offset 00000h 00001h (2) (BA+2)h 00004-Fh 00010h 0001Bh 00027h P
(3)
Description Manufacturer Code Device Code Block Status register Block-specific information Reserved Reserved for vendor-specific information CFI query identification string Command set ID and vendor data offset System interface information Device timing & voltage information Device geometry definition Flash device layout Vendor-defined additional information specific Primary Intel-specific Extended Query Table to the Primary Vendor Algorithm
Sub-Section Name
(1)
NOTES: 1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. BA = Block Address beginning location (i.e., 08000h is block 1's beginning location when the block size is 32K-word). 3. Offset 15 defines "P" which points to the Primary Intel-specific Extended Query Table.
B.3
Block Status Register
The Block Status Register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. Block Erase Status (BSR.1) allows system software to determine the success of the last block erase operation. BSR.1 can be used just after power-up to verify that the VCC supply was not accidentally removed during an erase operation.
Table 34. Block Status Register
Offset Length Description (1) (BA+2)h 1 Block Lock Status Register BSR.0 Block lock status 0 = Unlocked 1 = Locked BSR.1 Block lock-down status 0 = Not locked down 1 = Locked down BSR 2-7: Reserved for future use Add. Value BA+2 --00 or --01 BA+2 (bit 0): 0 or 1
BA+2 (bit 1): 0 or 1
BA+2
(bit 2-7): 0
NOTES: 1. BA = Block Address beginning location (i.e., 08000h is block 1's beginning location when the block size is 32K-word).
B.4
CFI Query Identification String
The Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s).
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Intel(R) Wireless Flash Memory (W18)
Table 35. CFI Identification
Offset 10h Length 3 Description Query-unique ASCII string "QRY" Hex Add. Code Value 10: --51 "Q" 11: --52 "R" 12: --59 "Y" 13: --03 14: --00 15: --39 16: --00 17: --00 18: --00 19: --00 1A: --00
13h 15h 17h 19h
2 2 2 2
Primary vendor command set and control interface ID code. 16-bit ID code for vendor-specified algorithms Extended Query Table primary algorithm address Alternate vendor command set and control interface ID code. 0000h means no second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists
Table 36. System Interface Information
Offset 1Bh Length 1 Description VCC logic supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VCC logic supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VPP [programming] supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts VPP [programming] supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts "n" such that typical single word program time-out = 2n -sec n "n" such that typical max. buffer write time-out = 2 -sec n "n" such that typical block erase time-out = 2 m-sec n "n" such that typical full chip erase time-out = 2 m-sec n "n" such that maximum word program time-out = 2 times typical n "n" such that maximum buffer write time-out = 2 times typical n "n" such that maximum block erase time-out = 2 times typical n "n" such that maximum chip erase time-out = 2 times typical Hex Add. Code Value 1B: --17 1.7V
1Ch
1
1C:
--19
1.9V
1Dh
1
1D:
--B4
11.4V
1Eh
1
1E:
--C6 12.6V
1Fh 20h 21h 22h 23h 24h 25h 26h
1 1 1 1 1 1 1 1
1F: 20: 21: 22: 23: 24: 25: 26:
--04 16s --00 NA --0A 1s --00 NA --04 256s --00 NA --03 8s --00 NA
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B.5
Device Geometry Definition
Offset 27h Length Description n "n" such that device size = 2 in number of bytes 1 Flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table:
7 6 5 4 3 2 1 0
Table 37. Device Geometry Definition
Code 27:
See table below
28h
2
--
15
--
14
--
13
--
12
x64
11
x32
10
x16
9
x8
8
28: 29: 2A: 2B: 2C:
--01 --00 --00 --00
x16
2Ah 2Ch
2 1
-- -- -- -- -- -- -- -- n "n" such that maximum number of bytes in write buffer = 2 Number of erase block regions (x) within device: 1. x = 0 means no erase blocking; the device erases in bulk 2. x specifies the number of device regions with one or more contiguous same-size erase blocks. 3. Symmetrically blocked partitions have one blocking region Erase Block Region 1 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes Erase Block Region 2 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes Reserved for future erase block region information
0
See table below
2Dh
4
31h
4
35h
4
2D: 2E: 2F: 30: 31: 32: 33: 34: 35: 36: 37: 38:
See table below
See table below
See table below
Address 27: 28: 29: 2A: 2B: 2C: 2D: 2E: 2F: 30: 31: 32: 33: 34: 35: 36: 37: 38:
32 Mbit -B -T --16 --16 --01 --01 --00 --00 --00 --00 --00 --00 --02 --02 --07 --3E --00 --00 --20 --00 --00 --01 --07 --3E --00 --00 --20 --00 --00 --01 --00 --00 --00 --00 --00 --00 --00 --00
64 Mbit -B -T --17 --17 --01 --01 --00 --00 --00 --00 --00 --00 --02 --02 --07 --7E --00 --00 --20 --00 --00 --01 --07 --7E --00 --00 --20 --00 --00 --01 --00 --00 --00 --00 --00 --00 --00 --00
128 Mbit -B -T --18 --18 --01 --01 --00 --00 --00 --00 --00 --00 --02 --02 --07 --FE --00 --00 --20 --00 --00 --01 --07 --FE --00 --00 --20 --00 --00 --01 --00 --00 --00 --00 --00 --00 --00 --00
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Intel(R) Wireless Flash Memory (W18)
B.6
Intel-Specific Extended Query Table
Offset(1) P = 39h (P+0)h (P+1)h (P+2)h (P+3)h (P+4)h (P+5)h (P+6)h (P+7)h (P+8)h Length 3 Description (Optional flash features and commands) Primary extended query table Unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Optional feature and command support (1=yes, 0=no) bits 10-31 are reserved; undefined bits are "0." If bit 31 is "1" then another 31 bit field of Optional features follows at the end of the bit-30 field. bit 0 Chip erase supported bit 1 Suspend erase supported bit 2 Suspend program supported bit 3 Legacy lock/unlock supported bit 4 Queued erase supported bit 5 Instant individual block locking supported bit 6 Protection bits supported bit 7 Pagemode read supported bit 8 Synchronous read supported bit 9 Simultaneous operations supported Supported functions after suspend: read Array, Status, Query Other supported operations are: bits 1-7 reserved; undefined bits are "0" bit 0 Program supported after erase suspend Block status register mask bits 2-15 are Reserved; undefined bits are "0" bit 0 Block Lock-Bit Status register active bit 1 Block Lock-Down Bit Status active VCC logic supply highest performance program/erase voltage bits 0-3 BCD value in 100 mV bits 4-7 BCD value in volts VPP optimum program/erase supply voltage bits 0-3 BCD value in 100 mV bits 4-7 HEX value in volts Hex Code Value --50 "P" --52 "R" --49 "I" --31 "1" --33 "3" --E6 --03 --00 --00 =0 No =1 Yes =1 Yes =0 No =0 No =1 Yes =1 Yes =1 Yes =1 Yes =1 Yes --01
Table 38. Primary Vendor-Specific Extended Query
Add. 39: 3A: 3B: 3C: 3D: 3E: 3F: 40: 41: bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 42:
1 1 4
(P+9)h
1
(P+A)h (P+B)h
2
(P+C)h
1
bit 0 43: 44: bit 0 bit 1 45:
=1 --03 --00 =1 =1 --18
Yes
Yes Yes 1.8V
(P+D)h
1
46:
--C0 12.0V
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Intel(R) Wireless Flash Memory (W18)
Table 39. Protection Register Information
Offset P = 39h (P+E)h
(1)
Length 1 4
(P+F)h (P+10)h (P+11)h (P+12)h
Description (Optional flash features and commands) Number of Protection register fields in JEDEC ID space. "00h," indicates that 256 protection fields are available Protection Field 1: Protection Description This field describes user-available One Time Programmable (OTP) Protection register bytes. Some are pre-programmed with device-unique serial numbers. Others are user programmable. Bits 0-15 point to the Protection register Lock byte, the section's first byte. The following bytes are factory pre-programmed and user-programmable. bits 0-7 = Lock/bytes Jedec-plane physical low address bits 8-15 = Lock/bytes Jedec-plane physical high address bits 16-23 = "n" such that 2n = factory pre-programmed bytes bits 24-31 = "n" such that 2n = user programmable bytes
Hex Add. Code Value 47: --01 1 48: 49: 4A: 4B: --80 --00 --03 --03 80h 00h 8 byte 8 byte
Table 40. Burst Read Information for Non-muxed Device
Offset P = 39h (P+13)h
(1)
Length 1
(P+14)h (P+15)h
1 1
(P+16)h (P+17)h (P+18)h
1 1 1
Description (Optional flash features and commands) Page Mode Read capability n bits 0-7 = "n" such that 2 HEX value represents the number of read-page bytes. See offset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. Number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. Synchronous mode read capability configuration 1 Bits 3-7 = Reserved n+1 bits 0-2 "n" such that 2 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device's burstable address space. This field's 3-bit value can be written directly to the Read Configuration Register bits 0-2 if the device is configured for its maximum word width. See offset 28h for word width to determine the burst data output width. Synchronous mode read capability configuration 2 Synchronous mode read capability configuration 3 Synchronous mode read capability configuration 4
Hex Add. Code Value 4C: --03 8 byte
4D: 4E:
--04 --01
4 4
4F: 50: 51:
--02 --03 --07
8 16 Cont
Table 41. Partition and Erase-block Region Information
Offset P = 39h Description Bottom Top (Optional flash features and commands) (P+19)h (P+19)h Number of device hardware-partition regions within the device. x = 0: a single hardware partition device (no fields follow). x specifies the number of device partition regions containing one or more contiguous erase block regions.
(1)
See table below Address Bot Top Len 1 52: 52:
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Intel(R) Wireless Flash Memory (W18)
Partition Region 1 Information
Offset P = 39h Description Bottom Top (Optional flash features and commands) (P+1A)h (P+1A)h Number of identical partitions within the partition region (P+1B)h (P+1B)h (P+1C)h (P+1C)h Number of program or erase operations allowed in a partition bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+1D)h (P+1D)h Simultaneous program or erase operations allowed in other partitions while a partition in this region is in Program mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+1E)h (P+1E)h Simultaneous program or erase operations allowed in other partitions while a partition in this region is in Erase mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+1F)h (P+1F)h Types of erase block regions in this Partition Region. x = 0 = no erase blocking; the Partition Region erases in bulk x = number of erase block regions w/ contiguous same-size erase blocks. Symmetrically blocked partitions have one blocking region. Partition size = (Type 1 blocks)x(Type 1 block sizes) + (Type 2 blocks)x(Type 2 block sizes) +...+ (Type n blocks)x(Type n block sizes) (P+20)h (P+20)h Partition Region 1 Erase Block Type 1 Information (P+21)h (P+21)h bits 0-15 = y, y+1 = number of identical-size erase blocks (P+22)h (P+22)h bits 16-31 = z, region erase block(s) size are z x 256 bytes (P+23)h (P+23)h (P+24)h (P+24)h Partition 1 (Erase Block Type 1) Minimum block erase cycles x 1000 (P+25)h (P+25)h (P+26)h (P+26)h Partition 1 (erase block Type 1) bits per cell; internal ECC bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ECC used" (1=yes, 0=no) bits 5-7 = reserve for future use (P+27)h (P+27)h Partition 1 (erase block Type 1) page mode and synchronous mode capabilities defined in Table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3-7 = reserved for future use (P+28)h Partition Region 1 Erase Block Type 2 Information (P+29)h bits 0-15 = y, y+1 = number of identical-size erase blocks (P+2A)h bits 16-31 = z, region erase block(s) size are z x 256 bytes (P+2B)h (bottom parameter device only) (P+2C)h Partition 1 (Erase block Type 2) (P+2D)h Minimum block erase cycles x 1000 Partition 1 (Erase block Type 2) bits per cell (P+2E)h bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ECC used" (1=yes, 0=no) bits 5-7 = reserve for future use Partition 1 (Erase block Type 2) pagemode and synchronous (P+2F)h mode capabilities defined in Table 10 bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3-7 = reserved for future use
(1)
See table below Address Bot Top Len 2 53: 53: 54: 54: 1 55: 55:
1
56:
56:
1
57:
57:
1
58:
58:
4
2 1
59: 5A: 5B: 5C: 5D: 5E: 5F:
59: 5A: 5B: 5C: 5D: 5E: 5F:
1
60:
60:
4
2 1
61: 62: 63: 64: 65: 66: 67:
1
68:
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Intel(R) Wireless Flash Memory (W18)
Partition Region 2 Information
Offset P = 39h Description Bottom Top (Optional flash features and commands) (P+30)h (P+28)h Number of identical partitions within the partition region (P+31)h (P+29)h (P+32)h (P+2A)h Number of program or erase operations allowed in a partition bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+33)h
(1)
See table below Address Bot Top Len 2 69: 61: 6A: 62: 1 6B: 63:
(P+34)h
(P+35)h
(P+36)h (P+37)h (P+38)h (P+39)h (P+3A)h (P+3B)h (P+3C)h
(P+3D)h
(P+3E)h (P+3F)h
(P+2B)h Simultaneous program or erase operations allowed in other 1 partitions while a partition in this region is in Program mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+2C)h Simultaneous program or erase operations allowed in other 1 partitions while a partition in this region is in Erase mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+2D)h Types of erase block regions in this Partition Region. 1 x = 0 = no erase blocking; the Partition Region erases in bulk x = number of erase block regions w/ contiguous same-size erase blocks. Symmetrically blocked partitions have one blocking region. Partition size = (Type 1 blocks)x(Type 1 block sizes) + (Type 2 blocks)x(Type 2 block sizes) +...+ (Type n blocks)x(Type n block sizes) (P+2E)h Partition Region 2 Erase Block Type 1 Information 4 (P+2F)h bits 0-15 = y, y+1 = number of identical-size erase blocks (P+30)h bits 16-31 = z, region erase block(s) size are z x 256 bytes (P+31)h (P+32)h Partition 2 (Erase block Type 1) 2 (P+33)h Minimum block erase cycles x 1000 (P+34)h Partition 2 (Erase block Type 1) bits per cell 1 bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ECC used" (1=yes, 0=no) bits 5-7 = reserve for future use (P+35)h Partition 2 (erase block Type 1) pagemode and synchronous 1 mode capabilities as defined in Table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3-7 = reserved for future use (P+36)h Partition Region 2 Erase Block Type 2 Information 4 (P+37)h bits 0-15 = y, y+1 = number of identical-size erase blocks (P+38)h bits 16-31 = z, region erase block(s) size are z x 256 bytes (P+39)h (P+3A)h Partition 2 (Erase Block Type 2) 2 (P+3B)h Minimum block erase cycles x 1000 (P+3C)h Partition 2 (Erase Block Type 2) bits per cell 1 bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ECC used" (1=yes, 0=no) bits 5-7 = reserved for future use (P+3D)h Partition 2 (Erase block Type 2) pagemode and synchronous 1 mode capabilities as defined in Table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3-7 = reserved for future use (P+3E)h Features Space definitions (Reserved for future use) TBD (P+3F)h Reserved for future use Resv'd
6C:
64:
6D:
65:
6E:
66:
6F: 70: 71: 72: 73: 74: 75:
67: 68: 69: 6A: 6B: 6C: 6D:
76:
6E:
6F: 70: 71: 72: 73: 74: 75:
76:
77: 78:
77: 78:
Datasheet
93
Intel(R) Wireless Flash Memory (W18)
Partition and Erase-block Region Information
Address 52: 53: 54: 55: 56: 57: 58: 59: 5A: 5B: 5C: 5D: 5E: 5F: 60: 61: 62: 63: 64: 65: 66: 67: 68: 69: 6A: 6B: 6C: 6D: 6E: 6F: 70: 71: 72: 73: 74: 75: 76: -B --02 --01 --00 --11 --00 --00 --02 --07 --00 --20 --00 --64 --00 --01 --03 --06 --00 --00 --01 --64 --00 --01 --03 --07 --00 --11 --00 --00 --01 --07 --00 --00 --01 --64 --00 --01 --03 32 Mbit -T --02 --07 --00 --11 --00 --00 --01 --07 --00 --00 --01 --64 --00 --01 --03 --01 --00 --11 --00 --00 --02 --06 --00 --00 --01 --64 --00 --01 --03 --07 --00 --20 --00 --64 --00 --01 --03 -B --02 --01 --00 --11 --00 --00 --02 --07 --00 --20 --00 --64 --00 --01 --03 --06 --00 --00 --01 --64 --00 --01 --03 --0F --00 --11 --00 --00 --01 --07 --00 --00 --01 --64 --00 --01 --03 64Mbit -T --02 --0F --00 --11 --00 --00 --01 --07 --00 --00 --01 --64 --00 --01 --03 --01 --00 --11 --00 --00 --02 --06 --00 --00 --01 --64 --00 --01 --03 --07 --00 --20 --00 --64 --00 --01 --03 128Mbit -B -T --02 --02 --01 --1F --00 --00 --11 --11 --00 --00 --00 --00 --02 --01 --07 --07 --00 --00 --20 --00 --00 --01 --64 --64 --00 --00 --01 --01 --03 --03 --06 --01 --00 --00 --00 --11 --01 --00 --64 --00 --00 --02 --01 --06 --03 --00 --1F --00 --00 --01 --11 --64 --00 --00 --00 --01 --01 --03 --07 --07 --00 --00 --00 --20 --01 --00 --64 --64 --00 --00 --01 --01 --03 --03
NOTES: 1. The variable P is a pointer which is defined at CFI offset 15h. 2. TPD - Top parameter device; BPD - Bottom parameter device. 3. Partition: Each partition is 4Mb in size. It can contain main blocks OR a combination of both main and parameter blocks. 4. Partition Region: Symmetrical partitions form a partition region. (there are two partition regions, A. contains all the partitions that are made up of main blocks only. B. contains the partition that is made up of the parameter and the main blocks.
94
Datasheet
Intel(R) Wireless Flash Memory (W18)
Appendix C Mechanical Specifications
C.1 W18 - .18 m Lithography
BGA*CSP Package Drawing and Dimensions
s
P in # 1 C o rn e r
Figure 38. 64-Mb
P in # 1 In d ic a to r
D
1
1 A B C D E F G
2
3
4
5
6
7
8 A B C D E F G
s2
8 7 6 5 4 3 2 1
E
e b
T o p V ie w - S ilico n b a ck s id e
C o m p le te In k M a rk N o t A1 A2 A
B o tto m V ie w - B u m p s id e U p
S e a ti P la n
Y
S id e
Millimeters Min 0.850 0.150 0.612 0.300 7.600 8.900 Inches Min 0.0335 0.0059 0.0241 0.0118 0.2992 0.3503
Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D Corner to Ball A1 Distance Along E
Symbol A A1 A2 b D E [e] N Y S1 S2
Nom
Max 1.000 0.812 0.400 7.800 9.100
Notes
Nom
Max 0.0394 0.0320 0.0157 0.3071 0.3583
0.712 0.350 7.700 9.000 0.750 56 1.225 2.250
0.0280 0.0138 0.3031 0.3543 0.0295 56 0.0482 0.0886
1.125 2.150
0.100 1.325 2.350
0.0443 0.0846
0.0039 0.0522 0.0925
Datasheet
95
Intel(R) Wireless Flash Memory (W18)
Figure 39. 32-Mb VFBGA Package Drawing
Ball A1 Corner D S1 Ball A1 Corner
1 A B C E D E F G
2
3
4
5
6
7
8 A B C D E
8
7
6
5
4
3
2
1
S2
e F G b To p View - Bump Side Down A1 A2 A S eating P lane Side V iew Note: Drawing not to scale Bottom View - Ball Side Up
Y
Figure 40. 128-Mb VFBGA Package Drawing
Ball A1 Corner D S1 Ball A1 Corner
1 A B C E D E F G H J
2
3
4
5
6
7
8
9
10 A B C D E F G H J
10
98
7
6
5
4
3
21
S2
e
b Bottom View - Ball Side Up
Top View - Bump Side Down
A1 A2 A Seating Plane Side View Note: Drawing not to scal e
Y
96
Datasheet
Intel(R) Wireless Flash Memory (W18)
Table 42. 32-Mbit and 128-Mbit VFBGA Package Dimensions
Millimeters Dimension Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width 32Mb Package Body Length32Mb Package Body Width 128Mb Package Body Length 128Mb Pitch Ball (Lead) Count 32Mb Ball (Lead) Count 128Mb Seating Plane Coplanarity Corner to Ball A1 Distance Along D 32Mb Corner to Ball A1 Distance Along E 32Mb Corner to Ball A1 Distance Along D 128Mb Corner to Ball A1 Distance Along E 128Mb Symbol Min A A1 A2 b D E D E [e] N N Y S1 S2 S1 S2 1.125 2.150 2.775 2.900 1.225 2.250 2.875 3.000 0.850 0.150 0.615 0.325 7.600 8.900 12.400 11.900 0.665 0.375 7.700 9.000 12.500 12.000 0.750 56 60 0.100 1.325 2.350 2.975 3.1000 0.0443 0.0846 0.1093 0.1142 0.0482 0.0886 0.1132 0.1181 0.715 0.425 7.800 9.100 12.600 12.100 Nom Max 1.000 Min 0.0335 0.0059 0.0242 0.0128 0.2992 0.3503 0.4882 0.4685 0.0262 0.0148 0.3031 0.3543 0.4921 0.4724 0.0295 56 60 0.0039 0.0522 0.0925 0.1171 0.1220 0.0281 0.0167 0.3071 0.3583 0.4961 0.4764 Nom Max 0.0394 Inches
Datasheet
97
Intel(R) Wireless Flash Memory (W18)
C.2
W18 - .13 m Lithography
64- and 128-Mb VF BGA*CSP Package Drawing
B all A 1 Corner D S1
Figure 41. 32-,
B all A 1 Corner
1 A B C E D E F G
2
3
4
5
6
7
8 A B C D E
8
7
6
5
4
3
2
1
S2
e F G
b
Top V iew - Bump S ide Dow n
A1 A2 A
Bottom Vie w - Ba ll Sid e Up
S eating P lane
Y
Table 43. 32-Mbit, 64-Mbit, and 128-Mbit VFBGA Package Dimensions
Millimeters Dimension Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width (32Mb, 64Mb) Package Body Width (128Mb) Package Body Length (32Mb, 64Mb, 128Mb) Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D (32Mb, 64Mb) Corner to Ball A1 Distance Along D (128Mb) Corner to Ball A1 Distance Along E (32Mb, 64Mb,128Mb) Symbol Min A A1 A2 b D D E [e] N Y S1 S1 S2 1.125 2.775 2.150 1.225 2.2875 2.250 0.325 7.600 10.900 8.900 0.150 0.665 0.375 7.700 11.000 9.000 0.750 56 0.100 1.325 2.975 2.350 0.0443 0.1093 0.0846 0.0482 0.1132 0.0886 0.425 7.800 11.100 9.100 0.0128 0.2992 0.4291 0.3504 Nom Max 1.000 0.0059 0.0262 0.0148 0.3031 0.4331 0.3543 0.0295 56 0.0039 0.0522 0.1171 0.0925 0.0167 0.3071 0.4370 0.3583 Min Nom Max 0.0394 Inches
98
Datasheet
Intel(R) Wireless Flash Memory (W18)
Figure 42. 128Mbit QUAD+ Package Drawing
A1 Index Mark
1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 S2 A B C D E F G H J K L M D A B C D E F G H J K L M b E e S1
Top View - Ball Down
A2 A1
Bottom View - Ball Up
A
Y
Drawing not to scale.
Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D
Symbol A A1 A2 b D E e N Y S1 S2
Min 0.200 0.325 9.900 7.900
Millimeters Nom Max 1.200 0.860 0.375 10.000 8.000 0.800 88 1.200 0.600
Notes
Min 0.0079
Inches Nom
Max 0.0472
0.425 10.100 8.100
0.0128 0.3898 0.3110
0.0339 0.0148 0.3937 0.3150 0.0315 88 0.0472 0.0236
0.0167 0.3976 0.3189
1.100 0.500
0.100 1.300 0.700
0.0433 0.0197
0.0039 0.0512 0.0276
Datasheet
99
Intel(R) Wireless Flash Memory (W18)
Appendix D Ordering Information
Figure 43. VF BGA and BGA Ordering Information
GE 2 8 F 6 4 0W1 8 TD6 0
Package:
GE = 0.75 mm VF BGA GT = 0.75 mm BGA* Access Speed (ns) (60,80)
Product Line Designator:
for all Intel Flash Products
Process Identifier: C = 0.18 m D = 0.13 m Parameter Location:
T = Top Parameter B = Bottom Parameter
Device Density:
320 = 32Mbit 640 = 64Mbit 128 = 128Mbit
Product Family:
W18 = Intel (R) Wireless Flash Memory
Figure 44. SCSP Ordering Information
Flash 1 & 2
RD 4 8 F 3 0 0 0W0 YBQ0
Flash 3 & 4
Flash 1
Flash 2
Flash 3
Flash 4
Package:
RD = SCSP, Leaded PF = SCSP, Pb-Free
Device Details:
0 = Initial Version
Ballout Indicator: Product Line:
48F = Flash Only Q= QUAD+
Parameter Location: Flash Density:
0 = No die 3 = 128 Mbit T = Top Parameter B = Bottom Parameter
Product Family Designator:
W = Intel(R) Wireless Flash Memory
Voltage: Y = 1.8 Volt I/O
100
Datasheet

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